OpenPtf  0.1
Open General purpose Low Level softwaer platform for MCUs
stm32l476xx.h
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1 
50 #ifndef __STM32L476xx_H
51 #define __STM32L476xx_H
52 
53 #ifdef __cplusplus
54  extern "C" {
55 #endif /* __cplusplus */
56 
64 #define __CM4_REV 0x0001
65 #define __MPU_PRESENT 1
66 #define __NVIC_PRIO_BITS 4
67 #define __Vendor_SysTickConfig 0
68 #define __FPU_PRESENT 1
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85  NonMaskableInt_IRQn = -14,
86  HardFault_IRQn = -13,
87  MemoryManagement_IRQn = -12,
88  BusFault_IRQn = -11,
89  UsageFault_IRQn = -10,
90  SVCall_IRQn = -5,
91  DebugMonitor_IRQn = -4,
92  PendSV_IRQn = -2,
93  SysTick_IRQn = -1,
94 /****** STM32 specific Interrupt Numbers **********************************************************************/
95  WWDG_IRQn = 0,
96  PVD_PVM_IRQn = 1,
97  TAMP_STAMP_IRQn = 2,
98  RTC_WKUP_IRQn = 3,
99  FLASH_IRQn = 4,
100  RCC_IRQn = 5,
101  EXTI0_IRQn = 6,
102  EXTI1_IRQn = 7,
103  EXTI2_IRQn = 8,
104  EXTI3_IRQn = 9,
105  EXTI4_IRQn = 10,
106  DMA1_Channel1_IRQn = 11,
107  DMA1_Channel2_IRQn = 12,
108  DMA1_Channel3_IRQn = 13,
109  DMA1_Channel4_IRQn = 14,
110  DMA1_Channel5_IRQn = 15,
111  DMA1_Channel6_IRQn = 16,
112  DMA1_Channel7_IRQn = 17,
113  ADC1_2_IRQn = 18,
114  CAN1_TX_IRQn = 19,
115  CAN1_RX0_IRQn = 20,
116  CAN1_RX1_IRQn = 21,
117  CAN1_SCE_IRQn = 22,
118  EXTI9_5_IRQn = 23,
119  TIM1_BRK_TIM15_IRQn = 24,
120  TIM1_UP_TIM16_IRQn = 25,
121  TIM1_TRG_COM_TIM17_IRQn = 26,
122  TIM1_CC_IRQn = 27,
123  TIM2_IRQn = 28,
124  TIM3_IRQn = 29,
125  TIM4_IRQn = 30,
126  I2C1_EV_IRQn = 31,
127  I2C1_ER_IRQn = 32,
128  I2C2_EV_IRQn = 33,
129  I2C2_ER_IRQn = 34,
130  SPI1_IRQn = 35,
131  SPI2_IRQn = 36,
132  USART1_IRQn = 37,
133  USART2_IRQn = 38,
134  USART3_IRQn = 39,
135  EXTI15_10_IRQn = 40,
136  RTC_Alarm_IRQn = 41,
137  DFSDM1_FLT3_IRQn = 42,
138  TIM8_BRK_IRQn = 43,
139  TIM8_UP_IRQn = 44,
140  TIM8_TRG_COM_IRQn = 45,
141  TIM8_CC_IRQn = 46,
142  ADC3_IRQn = 47,
143  FMC_IRQn = 48,
144  SDMMC1_IRQn = 49,
145  TIM5_IRQn = 50,
146  SPI3_IRQn = 51,
147  UART4_IRQn = 52,
148  UART5_IRQn = 53,
149  TIM6_DAC_IRQn = 54,
150  TIM7_IRQn = 55,
151  DMA2_Channel1_IRQn = 56,
152  DMA2_Channel2_IRQn = 57,
153  DMA2_Channel3_IRQn = 58,
154  DMA2_Channel4_IRQn = 59,
155  DMA2_Channel5_IRQn = 60,
156  DFSDM1_FLT0_IRQn = 61,
157  DFSDM1_FLT1_IRQn = 62,
158  DFSDM1_FLT2_IRQn = 63,
159  COMP_IRQn = 64,
160  LPTIM1_IRQn = 65,
161  LPTIM2_IRQn = 66,
162  OTG_FS_IRQn = 67,
163  DMA2_Channel6_IRQn = 68,
164  DMA2_Channel7_IRQn = 69,
165  LPUART1_IRQn = 70,
166  QUADSPI_IRQn = 71,
167  I2C3_EV_IRQn = 72,
168  I2C3_ER_IRQn = 73,
169  SAI1_IRQn = 74,
170  SAI2_IRQn = 75,
171  SWPMI1_IRQn = 76,
172  TSC_IRQn = 77,
173  LCD_IRQn = 78,
174  RNG_IRQn = 80,
175  FPU_IRQn = 81
176 } IRQn_Type;
177 
182 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
183 #include "system_stm32l4xx.h"
184 #include <stdint.h>
185 
194 typedef struct
195 {
196  __IO uint32_t ISR;
197  __IO uint32_t IER;
198  __IO uint32_t CR;
199  __IO uint32_t CFGR;
200  __IO uint32_t CFGR2;
201  __IO uint32_t SMPR1;
202  __IO uint32_t SMPR2;
203  uint32_t RESERVED1;
204  __IO uint32_t TR1;
205  __IO uint32_t TR2;
206  __IO uint32_t TR3;
207  uint32_t RESERVED2;
208  __IO uint32_t SQR1;
209  __IO uint32_t SQR2;
210  __IO uint32_t SQR3;
211  __IO uint32_t SQR4;
212  __IO uint32_t DR;
213  uint32_t RESERVED3;
214  uint32_t RESERVED4;
215  __IO uint32_t JSQR;
216  uint32_t RESERVED5[4];
217  __IO uint32_t OFR1;
218  __IO uint32_t OFR2;
219  __IO uint32_t OFR3;
220  __IO uint32_t OFR4;
221  uint32_t RESERVED6[4];
222  __IO uint32_t JDR1;
223  __IO uint32_t JDR2;
224  __IO uint32_t JDR3;
225  __IO uint32_t JDR4;
226  uint32_t RESERVED7[4];
227  __IO uint32_t AWD2CR;
228  __IO uint32_t AWD3CR;
229  uint32_t RESERVED8;
230  uint32_t RESERVED9;
231  __IO uint32_t DIFSEL;
232  __IO uint32_t CALFACT;
234 } ADC_TypeDef;
235 
236 typedef struct
237 {
238  __IO uint32_t CSR;
239  uint32_t RESERVED;
240  __IO uint32_t CCR;
241  __IO uint32_t CDR;
242 } ADC_Common_TypeDef;
243 
244 
249 typedef struct
250 {
251  __IO uint32_t TIR;
252  __IO uint32_t TDTR;
253  __IO uint32_t TDLR;
254  __IO uint32_t TDHR;
255 } CAN_TxMailBox_TypeDef;
256 
261 typedef struct
262 {
263  __IO uint32_t RIR;
264  __IO uint32_t RDTR;
265  __IO uint32_t RDLR;
266  __IO uint32_t RDHR;
267 } CAN_FIFOMailBox_TypeDef;
268 
273 typedef struct
274 {
275  __IO uint32_t FR1;
276  __IO uint32_t FR2;
277 } CAN_FilterRegister_TypeDef;
278 
283 typedef struct
284 {
285  __IO uint32_t MCR;
286  __IO uint32_t MSR;
287  __IO uint32_t TSR;
288  __IO uint32_t RF0R;
289  __IO uint32_t RF1R;
290  __IO uint32_t IER;
291  __IO uint32_t ESR;
292  __IO uint32_t BTR;
293  uint32_t RESERVED0[88];
294  CAN_TxMailBox_TypeDef sTxMailBox[3];
295  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
296  uint32_t RESERVED1[12];
297  __IO uint32_t FMR;
298  __IO uint32_t FM1R;
299  uint32_t RESERVED2;
300  __IO uint32_t FS1R;
301  uint32_t RESERVED3;
302  __IO uint32_t FFA1R;
303  uint32_t RESERVED4;
304  __IO uint32_t FA1R;
305  uint32_t RESERVED5[8];
306  CAN_FilterRegister_TypeDef sFilterRegister[28];
307 } CAN_TypeDef;
308 
309 
314 typedef struct
315 {
316  __IO uint32_t CSR;
317 } COMP_TypeDef;
318 
319 typedef struct
320 {
321  __IO uint32_t CSR;
322 } COMP_Common_TypeDef;
323 
328 typedef struct
329 {
330  __IO uint32_t DR;
331  __IO uint8_t IDR;
332  uint8_t RESERVED0;
333  uint16_t RESERVED1;
334  __IO uint32_t CR;
335  uint32_t RESERVED2;
336  __IO uint32_t INIT;
337  __IO uint32_t POL;
338 } CRC_TypeDef;
339 
344 typedef struct
345 {
346  __IO uint32_t CR;
347  __IO uint32_t SWTRIGR;
348  __IO uint32_t DHR12R1;
349  __IO uint32_t DHR12L1;
350  __IO uint32_t DHR8R1;
351  __IO uint32_t DHR12R2;
352  __IO uint32_t DHR12L2;
353  __IO uint32_t DHR8R2;
354  __IO uint32_t DHR12RD;
355  __IO uint32_t DHR12LD;
356  __IO uint32_t DHR8RD;
357  __IO uint32_t DOR1;
358  __IO uint32_t DOR2;
359  __IO uint32_t SR;
360  __IO uint32_t CCR;
361  __IO uint32_t MCR;
362  __IO uint32_t SHSR1;
363  __IO uint32_t SHSR2;
364  __IO uint32_t SHHR;
365  __IO uint32_t SHRR;
366 } DAC_TypeDef;
367 
371 typedef struct
372 {
373  __IO uint32_t FLTCR1;
374  __IO uint32_t FLTCR2;
375  __IO uint32_t FLTISR;
376  __IO uint32_t FLTICR;
377  __IO uint32_t FLTJCHGR;
378  __IO uint32_t FLTFCR;
379  __IO uint32_t FLTJDATAR;
380  __IO uint32_t FLTRDATAR;
381  __IO uint32_t FLTAWHTR;
382  __IO uint32_t FLTAWLTR;
383  __IO uint32_t FLTAWSR;
384  __IO uint32_t FLTAWCFR;
385  __IO uint32_t FLTEXMAX;
386  __IO uint32_t FLTEXMIN;
387  __IO uint32_t FLTCNVTIMR;
388 } DFSDM_Filter_TypeDef;
389 
393 typedef struct
394 {
395  __IO uint32_t CHCFGR1;
396  __IO uint32_t CHCFGR2;
397  __IO uint32_t CHAWSCDR;
399  __IO uint32_t CHWDATAR;
400  __IO uint32_t CHDATINR;
401 } DFSDM_Channel_TypeDef;
402 
407 typedef struct
408 {
409  __IO uint32_t IDCODE;
410  __IO uint32_t CR;
411  __IO uint32_t APB1FZR1;
412  __IO uint32_t APB1FZR2;
413  __IO uint32_t APB2FZ;
414 } DBGMCU_TypeDef;
415 
416 
421 typedef struct
422 {
423  __IO uint32_t CCR;
424  __IO uint32_t CNDTR;
425  __IO uint32_t CPAR;
426  __IO uint32_t CMAR;
427 } DMA_Channel_TypeDef;
428 
429 typedef struct
430 {
431  __IO uint32_t ISR;
432  __IO uint32_t IFCR;
433 } DMA_TypeDef;
434 
435 typedef struct
436 {
437  __IO uint32_t CSELR;
438 } DMA_Request_TypeDef;
439 
440 /* Legacy define */
441 #define DMA_request_TypeDef DMA_Request_TypeDef
442 
443 
448 typedef struct
449 {
450  __IO uint32_t IMR1;
451  __IO uint32_t EMR1;
452  __IO uint32_t RTSR1;
453  __IO uint32_t FTSR1;
454  __IO uint32_t SWIER1;
455  __IO uint32_t PR1;
456  uint32_t RESERVED1;
457  uint32_t RESERVED2;
458  __IO uint32_t IMR2;
459  __IO uint32_t EMR2;
460  __IO uint32_t RTSR2;
461  __IO uint32_t FTSR2;
462  __IO uint32_t SWIER2;
463  __IO uint32_t PR2;
464 } EXTI_TypeDef;
465 
466 
471 typedef struct
472 {
473  __IO uint32_t CSSA;
474  __IO uint32_t CSL;
475  __IO uint32_t NVDSSA;
476  __IO uint32_t NVDSL;
477  __IO uint32_t VDSSA ;
478  __IO uint32_t VDSL ;
479  uint32_t RESERVED1;
480  uint32_t RESERVED2;
481  __IO uint32_t CR ;
482 } FIREWALL_TypeDef;
483 
484 
489 typedef struct
490 {
491  __IO uint32_t ACR;
492  __IO uint32_t PDKEYR;
493  __IO uint32_t KEYR;
494  __IO uint32_t OPTKEYR;
495  __IO uint32_t SR;
496  __IO uint32_t CR;
497  __IO uint32_t ECCR;
498  __IO uint32_t RESERVED1;
499  __IO uint32_t OPTR;
500  __IO uint32_t PCROP1SR;
501  __IO uint32_t PCROP1ER;
502  __IO uint32_t WRP1AR;
503  __IO uint32_t WRP1BR;
504  uint32_t RESERVED2[4];
505  __IO uint32_t PCROP2SR;
506  __IO uint32_t PCROP2ER;
507  __IO uint32_t WRP2AR;
508  __IO uint32_t WRP2BR;
509 } FLASH_TypeDef;
510 
511 
516 typedef struct
517 {
518  __IO uint32_t BTCR[8];
519 } FMC_Bank1_TypeDef;
520 
525 typedef struct
526 {
527  __IO uint32_t BWTR[7];
528 } FMC_Bank1E_TypeDef;
529 
534 typedef struct
535 {
536  __IO uint32_t PCR;
537  __IO uint32_t SR;
538  __IO uint32_t PMEM;
539  __IO uint32_t PATT;
540  uint32_t RESERVED0;
541  __IO uint32_t ECCR;
542 } FMC_Bank3_TypeDef;
543 
548 typedef struct
549 {
550  __IO uint32_t MODER;
551  __IO uint32_t OTYPER;
552  __IO uint32_t OSPEEDR;
553  __IO uint32_t PUPDR;
554  __IO uint32_t IDR;
555  __IO uint32_t ODR;
556  __IO uint32_t BSRR;
557  __IO uint32_t LCKR;
558  __IO uint32_t AFR[2];
559  __IO uint32_t BRR;
560  __IO uint32_t ASCR;
562 } GPIO_TypeDef;
563 
564 
569 typedef struct
570 {
571  __IO uint32_t CR1;
572  __IO uint32_t CR2;
573  __IO uint32_t OAR1;
574  __IO uint32_t OAR2;
575  __IO uint32_t TIMINGR;
576  __IO uint32_t TIMEOUTR;
577  __IO uint32_t ISR;
578  __IO uint32_t ICR;
579  __IO uint32_t PECR;
580  __IO uint32_t RXDR;
581  __IO uint32_t TXDR;
582 } I2C_TypeDef;
583 
588 typedef struct
589 {
590  __IO uint32_t KR;
591  __IO uint32_t PR;
592  __IO uint32_t RLR;
593  __IO uint32_t SR;
594  __IO uint32_t WINR;
595 } IWDG_TypeDef;
596 
601 typedef struct
602 {
603  __IO uint32_t CR;
604  __IO uint32_t FCR;
605  __IO uint32_t SR;
606  __IO uint32_t CLR;
607  uint32_t RESERVED;
608  __IO uint32_t RAM[16];
609 } LCD_TypeDef;
610 
614 typedef struct
615 {
616  __IO uint32_t ISR;
617  __IO uint32_t ICR;
618  __IO uint32_t IER;
619  __IO uint32_t CFGR;
620  __IO uint32_t CR;
621  __IO uint32_t CMP;
622  __IO uint32_t ARR;
623  __IO uint32_t CNT;
624  __IO uint32_t OR;
625 } LPTIM_TypeDef;
626 
631 typedef struct
632 {
633  __IO uint32_t CSR;
634  __IO uint32_t OTR;
635  __IO uint32_t LPOTR;
636 } OPAMP_TypeDef;
637 
638 typedef struct
639 {
640  __IO uint32_t CSR;
641 } OPAMP_Common_TypeDef;
642 
647 typedef struct
648 {
649  __IO uint32_t CR1;
650  __IO uint32_t CR2;
651  __IO uint32_t CR3;
652  __IO uint32_t CR4;
653  __IO uint32_t SR1;
654  __IO uint32_t SR2;
655  __IO uint32_t SCR;
656  uint32_t RESERVED;
657  __IO uint32_t PUCRA;
658  __IO uint32_t PDCRA;
659  __IO uint32_t PUCRB;
660  __IO uint32_t PDCRB;
661  __IO uint32_t PUCRC;
662  __IO uint32_t PDCRC;
663  __IO uint32_t PUCRD;
664  __IO uint32_t PDCRD;
665  __IO uint32_t PUCRE;
666  __IO uint32_t PDCRE;
667  __IO uint32_t PUCRF;
668  __IO uint32_t PDCRF;
669  __IO uint32_t PUCRG;
670  __IO uint32_t PDCRG;
671  __IO uint32_t PUCRH;
672  __IO uint32_t PDCRH;
673 } PWR_TypeDef;
674 
675 
680 typedef struct
681 {
682  __IO uint32_t CR;
683  __IO uint32_t DCR;
684  __IO uint32_t SR;
685  __IO uint32_t FCR;
686  __IO uint32_t DLR;
687  __IO uint32_t CCR;
688  __IO uint32_t AR;
689  __IO uint32_t ABR;
690  __IO uint32_t DR;
691  __IO uint32_t PSMKR;
692  __IO uint32_t PSMAR;
693  __IO uint32_t PIR;
694  __IO uint32_t LPTR;
695 } QUADSPI_TypeDef;
696 
697 
702 typedef struct
703 {
704  __IO uint32_t CR;
705  __IO uint32_t ICSCR;
706  __IO uint32_t CFGR;
707  __IO uint32_t PLLCFGR;
708  __IO uint32_t PLLSAI1CFGR;
709  __IO uint32_t PLLSAI2CFGR;
710  __IO uint32_t CIER;
711  __IO uint32_t CIFR;
712  __IO uint32_t CICR;
713  uint32_t RESERVED0;
714  __IO uint32_t AHB1RSTR;
715  __IO uint32_t AHB2RSTR;
716  __IO uint32_t AHB3RSTR;
717  uint32_t RESERVED1;
718  __IO uint32_t APB1RSTR1;
719  __IO uint32_t APB1RSTR2;
720  __IO uint32_t APB2RSTR;
721  uint32_t RESERVED2;
722  __IO uint32_t AHB1ENR;
723  __IO uint32_t AHB2ENR;
724  __IO uint32_t AHB3ENR;
725  uint32_t RESERVED3;
726  __IO uint32_t APB1ENR1;
727  __IO uint32_t APB1ENR2;
728  __IO uint32_t APB2ENR;
729  uint32_t RESERVED4;
730  __IO uint32_t AHB1SMENR;
731  __IO uint32_t AHB2SMENR;
732  __IO uint32_t AHB3SMENR;
733  uint32_t RESERVED5;
734  __IO uint32_t APB1SMENR1;
735  __IO uint32_t APB1SMENR2;
736  __IO uint32_t APB2SMENR;
737  uint32_t RESERVED6;
738  __IO uint32_t CCIPR;
739  uint32_t RESERVED7;
740  __IO uint32_t BDCR;
741  __IO uint32_t CSR;
742 } RCC_TypeDef;
743 
748 typedef struct
749 {
750  __IO uint32_t TR;
751  __IO uint32_t DR;
752  __IO uint32_t CR;
753  __IO uint32_t ISR;
754  __IO uint32_t PRER;
755  __IO uint32_t WUTR;
756  uint32_t reserved;
757  __IO uint32_t ALRMAR;
758  __IO uint32_t ALRMBR;
759  __IO uint32_t WPR;
760  __IO uint32_t SSR;
761  __IO uint32_t SHIFTR;
762  __IO uint32_t TSTR;
763  __IO uint32_t TSDR;
764  __IO uint32_t TSSSR;
765  __IO uint32_t CALR;
766  __IO uint32_t TAMPCR;
767  __IO uint32_t ALRMASSR;
768  __IO uint32_t ALRMBSSR;
769  __IO uint32_t OR;
770  __IO uint32_t BKP0R;
771  __IO uint32_t BKP1R;
772  __IO uint32_t BKP2R;
773  __IO uint32_t BKP3R;
774  __IO uint32_t BKP4R;
775  __IO uint32_t BKP5R;
776  __IO uint32_t BKP6R;
777  __IO uint32_t BKP7R;
778  __IO uint32_t BKP8R;
779  __IO uint32_t BKP9R;
780  __IO uint32_t BKP10R;
781  __IO uint32_t BKP11R;
782  __IO uint32_t BKP12R;
783  __IO uint32_t BKP13R;
784  __IO uint32_t BKP14R;
785  __IO uint32_t BKP15R;
786  __IO uint32_t BKP16R;
787  __IO uint32_t BKP17R;
788  __IO uint32_t BKP18R;
789  __IO uint32_t BKP19R;
790  __IO uint32_t BKP20R;
791  __IO uint32_t BKP21R;
792  __IO uint32_t BKP22R;
793  __IO uint32_t BKP23R;
794  __IO uint32_t BKP24R;
795  __IO uint32_t BKP25R;
796  __IO uint32_t BKP26R;
797  __IO uint32_t BKP27R;
798  __IO uint32_t BKP28R;
799  __IO uint32_t BKP29R;
800  __IO uint32_t BKP30R;
801  __IO uint32_t BKP31R;
802 } RTC_TypeDef;
803 
808 typedef struct
809 {
810  __IO uint32_t GCR;
811 } SAI_TypeDef;
812 
813 typedef struct
814 {
815  __IO uint32_t CR1;
816  __IO uint32_t CR2;
817  __IO uint32_t FRCR;
818  __IO uint32_t SLOTR;
819  __IO uint32_t IMR;
820  __IO uint32_t SR;
821  __IO uint32_t CLRFR;
822  __IO uint32_t DR;
823 } SAI_Block_TypeDef;
824 
825 
830 typedef struct
831 {
832  __IO uint32_t POWER;
833  __IO uint32_t CLKCR;
834  __IO uint32_t ARG;
835  __IO uint32_t CMD;
836  __I uint32_t RESPCMD;
837  __I uint32_t RESP1;
838  __I uint32_t RESP2;
839  __I uint32_t RESP3;
840  __I uint32_t RESP4;
841  __IO uint32_t DTIMER;
842  __IO uint32_t DLEN;
843  __IO uint32_t DCTRL;
844  __I uint32_t DCOUNT;
845  __I uint32_t STA;
846  __IO uint32_t ICR;
847  __IO uint32_t MASK;
848  uint32_t RESERVED0[2];
849  __I uint32_t FIFOCNT;
850  uint32_t RESERVED1[13];
851  __IO uint32_t FIFO;
852 } SDMMC_TypeDef;
853 
854 
859 typedef struct
860 {
861  __IO uint32_t CR1;
862  __IO uint32_t CR2;
863  __IO uint32_t SR;
864  __IO uint32_t DR;
865  __IO uint32_t CRCPR;
866  __IO uint32_t RXCRCR;
867  __IO uint32_t TXCRCR;
868 } SPI_TypeDef;
869 
870 
875 typedef struct
876 {
877  __IO uint32_t CR;
878  __IO uint32_t BRR;
879  uint32_t RESERVED1;
880  __IO uint32_t ISR;
881  __IO uint32_t ICR;
882  __IO uint32_t IER;
883  __IO uint32_t RFL;
884  __IO uint32_t TDR;
885  __IO uint32_t RDR;
886  __IO uint32_t OR;
887 } SWPMI_TypeDef;
888 
889 
894 typedef struct
895 {
896  __IO uint32_t MEMRMP;
897  __IO uint32_t CFGR1;
898  __IO uint32_t EXTICR[4];
899  __IO uint32_t SCSR;
900  __IO uint32_t CFGR2;
901  __IO uint32_t SWPR;
902  __IO uint32_t SKR;
903 } SYSCFG_TypeDef;
904 
905 
910 typedef struct
911 {
912  __IO uint32_t CR1;
913  __IO uint32_t CR2;
914  __IO uint32_t SMCR;
915  __IO uint32_t DIER;
916  __IO uint32_t SR;
917  __IO uint32_t EGR;
918  __IO uint32_t CCMR1;
919  __IO uint32_t CCMR2;
920  __IO uint32_t CCER;
921  __IO uint32_t CNT;
922  __IO uint32_t PSC;
923  __IO uint32_t ARR;
924  __IO uint32_t RCR;
925  __IO uint32_t CCR1;
926  __IO uint32_t CCR2;
927  __IO uint32_t CCR3;
928  __IO uint32_t CCR4;
929  __IO uint32_t BDTR;
930  __IO uint32_t DCR;
931  __IO uint32_t DMAR;
932  __IO uint32_t OR1;
933  __IO uint32_t CCMR3;
934  __IO uint32_t CCR5;
935  __IO uint32_t CCR6;
936  __IO uint32_t OR2;
937  __IO uint32_t OR3;
938 } TIM_TypeDef;
939 
940 
945 typedef struct
946 {
947  __IO uint32_t CR;
948  __IO uint32_t IER;
949  __IO uint32_t ICR;
950  __IO uint32_t ISR;
951  __IO uint32_t IOHCR;
952  uint32_t RESERVED1;
953  __IO uint32_t IOASCR;
954  uint32_t RESERVED2;
955  __IO uint32_t IOSCR;
956  uint32_t RESERVED3;
957  __IO uint32_t IOCCR;
958  uint32_t RESERVED4;
959  __IO uint32_t IOGCSR;
960  __IO uint32_t IOGXCR[8];
961 } TSC_TypeDef;
962 
967 typedef struct
968 {
969  __IO uint32_t CR1;
970  __IO uint32_t CR2;
971  __IO uint32_t CR3;
972  __IO uint32_t BRR;
973  __IO uint16_t GTPR;
974  uint16_t RESERVED2;
975  __IO uint32_t RTOR;
976  __IO uint16_t RQR;
977  uint16_t RESERVED3;
978  __IO uint32_t ISR;
979  __IO uint32_t ICR;
980  __IO uint16_t RDR;
981  uint16_t RESERVED4;
982  __IO uint16_t TDR;
983  uint16_t RESERVED5;
984 } USART_TypeDef;
985 
990 typedef struct
991 {
992  __IO uint32_t CSR;
993  __IO uint32_t CCR;
994 } VREFBUF_TypeDef;
995 
1000 typedef struct
1001 {
1002  __IO uint32_t CR;
1003  __IO uint32_t CFR;
1004  __IO uint32_t SR;
1005 } WWDG_TypeDef;
1006 
1011 typedef struct
1012 {
1013  __IO uint32_t CR;
1014  __IO uint32_t SR;
1015  __IO uint32_t DR;
1016 } RNG_TypeDef;
1017 
1021 typedef struct
1022 {
1023  __IO uint32_t GOTGCTL;
1024  __IO uint32_t GOTGINT;
1025  __IO uint32_t GAHBCFG;
1026  __IO uint32_t GUSBCFG;
1027  __IO uint32_t GRSTCTL;
1028  __IO uint32_t GINTSTS;
1029  __IO uint32_t GINTMSK;
1030  __IO uint32_t GRXSTSR;
1031  __IO uint32_t GRXSTSP;
1032  __IO uint32_t GRXFSIZ;
1033  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1034  __IO uint32_t HNPTXSTS;
1035  uint32_t Reserved30[2];
1036  __IO uint32_t GCCFG;
1037  __IO uint32_t CID;
1038  __IO uint32_t GSNPSID;
1039  __IO uint32_t GHWCFG1;
1040  __IO uint32_t GHWCFG2;
1041  __IO uint32_t GHWCFG3;
1042  uint32_t Reserved6;
1043  __IO uint32_t GLPMCFG;
1044  __IO uint32_t GPWRDN;
1045  __IO uint32_t GDFIFOCFG;
1046  __IO uint32_t GADPCTL;
1047  uint32_t Reserved43[39];
1048  __IO uint32_t HPTXFSIZ;
1049  __IO uint32_t DIEPTXF[0x0F];
1050 } USB_OTG_GlobalTypeDef;
1051 
1055 typedef struct
1056 {
1057  __IO uint32_t DCFG; /* dev Configuration Register 800h*/
1058  __IO uint32_t DCTL; /* dev Control Register 804h*/
1059  __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
1060  uint32_t Reserved0C; /* Reserved 80Ch*/
1061  __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
1062  __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
1063  __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
1064  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
1065  uint32_t Reserved20; /* Reserved 820h*/
1066  uint32_t Reserved24; /* Reserved 824h*/
1067  __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
1068  __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
1069  __IO uint32_t DTHRCTL; /* dev thr 830h*/
1070  __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
1071  __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
1072  __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
1073  uint32_t Reserved40; /* Reserved 840h*/
1074  __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
1075  uint32_t Reserved44[15]; /* Reserved 848-880h*/
1076  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
1077 } USB_OTG_DeviceTypeDef;
1078 
1082 typedef struct
1083 {
1084  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1085  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
1086  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
1087  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
1088  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
1089  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
1090  __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1091  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1092 } USB_OTG_INEndpointTypeDef;
1093 
1097 typedef struct
1098 {
1099  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1100  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1101  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1102  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1103  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1104  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1105  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1106 } USB_OTG_OUTEndpointTypeDef;
1107 
1111 typedef struct
1112 {
1113  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1114  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1115  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1116  uint32_t Reserved40C; /* Reserved 40Ch*/
1117  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1118  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1119  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1120 } USB_OTG_HostTypeDef;
1121 
1125 typedef struct
1126 {
1127  __IO uint32_t HCCHAR;
1128  __IO uint32_t HCSPLT;
1129  __IO uint32_t HCINT;
1130  __IO uint32_t HCINTMSK;
1131  __IO uint32_t HCTSIZ;
1132  __IO uint32_t HCDMA;
1133  uint32_t Reserved[2];
1134 } USB_OTG_HostChannelTypeDef;
1135 
1143 #define FLASH_BASE (0x08000000UL)
1144 #define SRAM1_BASE (0x20000000UL)
1145 #define SRAM2_BASE (0x10000000UL)
1146 #define PERIPH_BASE (0x40000000UL)
1147 #define FMC_BASE (0x60000000UL)
1148 #define QSPI_BASE (0x90000000UL)
1150 #define FMC_R_BASE (0xA0000000UL)
1151 #define QSPI_R_BASE (0xA0001000UL)
1152 #define SRAM1_BB_BASE (0x22000000UL)
1153 #define PERIPH_BB_BASE (0x42000000UL)
1155 /* Legacy defines */
1156 #define SRAM_BASE SRAM1_BASE
1157 #define SRAM_BB_BASE SRAM1_BB_BASE
1158 
1159 #define SRAM1_SIZE_MAX (0x00018000UL)
1160 #define SRAM2_SIZE (0x00008000UL)
1163 #define APB1PERIPH_BASE PERIPH_BASE
1164 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1165 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1166 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
1167 
1168 #define FMC_BANK1 FMC_BASE
1169 #define FMC_BANK1_1 FMC_BANK1
1170 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
1171 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
1172 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
1173 #define FMC_BANK3 (FMC_BASE + 0x20000000UL)
1174 
1176 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1177 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1178 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1179 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1180 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1181 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1182 #define LCD_BASE (APB1PERIPH_BASE + 0x2400UL)
1183 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1184 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1185 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1186 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1187 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1188 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1189 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1190 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1191 #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1192 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1193 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1194 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1195 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1196 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1197 #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1198 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
1199 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
1200 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL)
1201 #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL)
1202 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
1203 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
1204 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL)
1205 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
1206 
1207 
1209 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
1210 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
1211 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
1212 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
1213 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
1214 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL)
1215 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL)
1216 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1217 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1218 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
1219 #define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
1220 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
1221 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
1222 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
1223 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
1224 #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
1225 #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
1226 #define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL)
1227 #define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL)
1228 #define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL)
1229 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL)
1230 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL)
1231 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL)
1232 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL)
1233 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL)
1234 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL)
1235 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL)
1236 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL)
1237 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL)
1238 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL)
1239 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL)
1240 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL)
1241 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL)
1242 
1244 #define DMA1_BASE (AHB1PERIPH_BASE)
1245 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
1246 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
1247 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
1248 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1249 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL)
1250 
1251 
1252 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
1253 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
1254 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
1255 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
1256 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1257 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1258 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
1259 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
1260 
1261 
1262 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
1263 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
1264 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
1265 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
1266 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
1267 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
1268 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
1269 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
1270 
1271 
1273 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
1274 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
1275 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
1276 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
1277 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
1278 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
1279 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
1280 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL)
1281 
1282 #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL)
1283 
1284 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
1285 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL)
1286 #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL)
1287 #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
1288 
1289 
1290 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
1291 
1292 
1294 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1295 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1296 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1297 
1298 /* Debug MCU registers base address */
1299 #define DBGMCU_BASE (0xE0042000UL)
1300 
1302 #define USB_OTG_FS_PERIPH_BASE (0x50000000UL)
1303 
1304 #define USB_OTG_GLOBAL_BASE (0x00000000UL)
1305 #define USB_OTG_DEVICE_BASE (0x00000800UL)
1306 #define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL)
1307 #define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL)
1308 #define USB_OTG_EP_REG_SIZE (0x00000020UL)
1309 #define USB_OTG_HOST_BASE (0x00000400UL)
1310 #define USB_OTG_HOST_PORT_BASE (0x00000440UL)
1311 #define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL)
1312 #define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL)
1313 #define USB_OTG_PCGCCTL_BASE (0x00000E00UL)
1314 #define USB_OTG_FIFO_BASE (0x00001000UL)
1315 #define USB_OTG_FIFO_SIZE (0x00001000UL)
1316 
1317 
1318 #define PACKAGE_BASE (0x1FFF7500UL)
1319 #define UID_BASE (0x1FFF7590UL)
1320 #define FLASHSIZE_BASE (0x1FFF75E0UL)
1328 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1329 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1330 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1331 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1332 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1333 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1334 #define LCD ((LCD_TypeDef *) LCD_BASE)
1335 #define RTC ((RTC_TypeDef *) RTC_BASE)
1336 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1337 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1338 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1339 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1340 #define USART2 ((USART_TypeDef *) USART2_BASE)
1341 #define USART3 ((USART_TypeDef *) USART3_BASE)
1342 #define UART4 ((USART_TypeDef *) UART4_BASE)
1343 #define UART5 ((USART_TypeDef *) UART5_BASE)
1344 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1345 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1346 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1347 #define CAN ((CAN_TypeDef *) CAN1_BASE)
1348 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1349 #define PWR ((PWR_TypeDef *) PWR_BASE)
1350 #define DAC ((DAC_TypeDef *) DAC1_BASE)
1351 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1352 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1353 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1354 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1355 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1356 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1357 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1358 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1359 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1360 
1361 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1362 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1363 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1364 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1365 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1366 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1367 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1368 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1369 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1370 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1371 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1372 #define USART1 ((USART_TypeDef *) USART1_BASE)
1373 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1374 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1375 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1376 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1377 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1378 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1379 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1380 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1381 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1382 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1383 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1384 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1385 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1386 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1387 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1388 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1389 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1390 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1391 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1392 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1393 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1394 /* Aliases to keep compatibility after DFSDM renaming */
1395 #define DFSDM_Channel0 DFSDM1_Channel0
1396 #define DFSDM_Channel1 DFSDM1_Channel1
1397 #define DFSDM_Channel2 DFSDM1_Channel2
1398 #define DFSDM_Channel3 DFSDM1_Channel3
1399 #define DFSDM_Channel4 DFSDM1_Channel4
1400 #define DFSDM_Channel5 DFSDM1_Channel5
1401 #define DFSDM_Channel6 DFSDM1_Channel6
1402 #define DFSDM_Channel7 DFSDM1_Channel7
1403 #define DFSDM_Filter0 DFSDM1_Filter0
1404 #define DFSDM_Filter1 DFSDM1_Filter1
1405 #define DFSDM_Filter2 DFSDM1_Filter2
1406 #define DFSDM_Filter3 DFSDM1_Filter3
1407 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1408 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1409 #define RCC ((RCC_TypeDef *) RCC_BASE)
1410 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1411 #define CRC ((CRC_TypeDef *) CRC_BASE)
1412 #define TSC ((TSC_TypeDef *) TSC_BASE)
1413 
1414 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1415 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1416 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1417 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1418 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1419 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1420 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1421 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1422 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1423 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1424 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1425 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1426 #define RNG ((RNG_TypeDef *) RNG_BASE)
1427 
1428 
1429 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1430 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1431 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1432 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1433 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1434 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1435 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1436 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1437 
1438 
1439 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1440 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1441 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1442 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1443 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1444 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1445 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1446 #define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1447 
1448 
1449 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1450 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1451 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1452 
1453 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1454 
1455 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1456 
1457 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1458 
1470 /******************************************************************************/
1471 /* Peripheral Registers_Bits_Definition */
1472 /******************************************************************************/
1473 
1474 /******************************************************************************/
1475 /* */
1476 /* Analog to Digital Converter */
1477 /* */
1478 /******************************************************************************/
1479 
1480 /*
1481  * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1482  */
1483 #define ADC_MULTIMODE_SUPPORT
1485 /******************** Bit definition for ADC_ISR register *******************/
1486 #define ADC_ISR_ADRDY_Pos (0U)
1487 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
1488 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
1489 #define ADC_ISR_EOSMP_Pos (1U)
1490 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
1491 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
1492 #define ADC_ISR_EOC_Pos (2U)
1493 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
1494 #define ADC_ISR_EOC ADC_ISR_EOC_Msk
1495 #define ADC_ISR_EOS_Pos (3U)
1496 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
1497 #define ADC_ISR_EOS ADC_ISR_EOS_Msk
1498 #define ADC_ISR_OVR_Pos (4U)
1499 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
1500 #define ADC_ISR_OVR ADC_ISR_OVR_Msk
1501 #define ADC_ISR_JEOC_Pos (5U)
1502 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
1503 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
1504 #define ADC_ISR_JEOS_Pos (6U)
1505 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
1506 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
1507 #define ADC_ISR_AWD1_Pos (7U)
1508 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
1509 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
1510 #define ADC_ISR_AWD2_Pos (8U)
1511 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
1512 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
1513 #define ADC_ISR_AWD3_Pos (9U)
1514 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
1515 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
1516 #define ADC_ISR_JQOVF_Pos (10U)
1517 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
1518 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
1520 /******************** Bit definition for ADC_IER register *******************/
1521 #define ADC_IER_ADRDYIE_Pos (0U)
1522 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
1523 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
1524 #define ADC_IER_EOSMPIE_Pos (1U)
1525 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
1526 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
1527 #define ADC_IER_EOCIE_Pos (2U)
1528 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
1529 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
1530 #define ADC_IER_EOSIE_Pos (3U)
1531 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
1532 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
1533 #define ADC_IER_OVRIE_Pos (4U)
1534 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
1535 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
1536 #define ADC_IER_JEOCIE_Pos (5U)
1537 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
1538 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
1539 #define ADC_IER_JEOSIE_Pos (6U)
1540 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
1541 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
1542 #define ADC_IER_AWD1IE_Pos (7U)
1543 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
1544 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
1545 #define ADC_IER_AWD2IE_Pos (8U)
1546 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
1547 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
1548 #define ADC_IER_AWD3IE_Pos (9U)
1549 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
1550 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
1551 #define ADC_IER_JQOVFIE_Pos (10U)
1552 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
1553 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
1555 /* Legacy defines */
1556 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1557 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1558 #define ADC_IER_EOC (ADC_IER_EOCIE)
1559 #define ADC_IER_EOS (ADC_IER_EOSIE)
1560 #define ADC_IER_OVR (ADC_IER_OVRIE)
1561 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
1562 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
1563 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1564 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1565 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1566 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1567 
1568 /******************** Bit definition for ADC_CR register ********************/
1569 #define ADC_CR_ADEN_Pos (0U)
1570 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
1571 #define ADC_CR_ADEN ADC_CR_ADEN_Msk
1572 #define ADC_CR_ADDIS_Pos (1U)
1573 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
1574 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
1575 #define ADC_CR_ADSTART_Pos (2U)
1576 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
1577 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
1578 #define ADC_CR_JADSTART_Pos (3U)
1579 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
1580 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
1581 #define ADC_CR_ADSTP_Pos (4U)
1582 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
1583 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
1584 #define ADC_CR_JADSTP_Pos (5U)
1585 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
1586 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
1587 #define ADC_CR_ADVREGEN_Pos (28U)
1588 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
1589 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
1590 #define ADC_CR_DEEPPWD_Pos (29U)
1591 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
1592 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
1593 #define ADC_CR_ADCALDIF_Pos (30U)
1594 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
1595 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
1596 #define ADC_CR_ADCAL_Pos (31U)
1597 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
1598 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
1600 /******************** Bit definition for ADC_CFGR register ******************/
1601 #define ADC_CFGR_DMAEN_Pos (0U)
1602 #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)
1603 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk
1604 #define ADC_CFGR_DMACFG_Pos (1U)
1605 #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)
1606 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk
1608 #define ADC_CFGR_RES_Pos (3U)
1609 #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)
1610 #define ADC_CFGR_RES ADC_CFGR_RES_Msk
1611 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
1612 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
1614 #define ADC_CFGR_ALIGN_Pos (5U)
1615 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)
1616 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk
1618 #define ADC_CFGR_EXTSEL_Pos (6U)
1619 #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos)
1620 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
1621 #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)
1622 #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)
1623 #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)
1624 #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)
1626 #define ADC_CFGR_EXTEN_Pos (10U)
1627 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
1628 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
1629 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
1630 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
1632 #define ADC_CFGR_OVRMOD_Pos (12U)
1633 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
1634 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
1635 #define ADC_CFGR_CONT_Pos (13U)
1636 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
1637 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
1638 #define ADC_CFGR_AUTDLY_Pos (14U)
1639 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
1640 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
1642 #define ADC_CFGR_DISCEN_Pos (16U)
1643 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
1644 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
1646 #define ADC_CFGR_DISCNUM_Pos (17U)
1647 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
1648 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
1649 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
1650 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
1651 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
1653 #define ADC_CFGR_JDISCEN_Pos (20U)
1654 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
1655 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
1656 #define ADC_CFGR_JQM_Pos (21U)
1657 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
1658 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
1659 #define ADC_CFGR_AWD1SGL_Pos (22U)
1660 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
1661 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
1662 #define ADC_CFGR_AWD1EN_Pos (23U)
1663 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
1664 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
1665 #define ADC_CFGR_JAWD1EN_Pos (24U)
1666 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
1667 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
1668 #define ADC_CFGR_JAUTO_Pos (25U)
1669 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
1670 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
1672 #define ADC_CFGR_AWD1CH_Pos (26U)
1673 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
1674 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
1675 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
1676 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
1677 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
1678 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
1679 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
1681 #define ADC_CFGR_JQDIS_Pos (31U)
1682 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
1683 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
1685 /******************** Bit definition for ADC_CFGR2 register *****************/
1686 #define ADC_CFGR2_ROVSE_Pos (0U)
1687 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
1688 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
1689 #define ADC_CFGR2_JOVSE_Pos (1U)
1690 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
1691 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
1693 #define ADC_CFGR2_OVSR_Pos (2U)
1694 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)
1695 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
1696 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)
1697 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)
1698 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)
1700 #define ADC_CFGR2_OVSS_Pos (5U)
1701 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
1702 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
1703 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
1704 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
1705 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
1706 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
1708 #define ADC_CFGR2_TROVS_Pos (9U)
1709 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
1710 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
1711 #define ADC_CFGR2_ROVSM_Pos (10U)
1712 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
1713 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
1715 /******************** Bit definition for ADC_SMPR1 register *****************/
1716 #define ADC_SMPR1_SMP0_Pos (0U)
1717 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
1718 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
1719 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
1720 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
1721 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
1723 #define ADC_SMPR1_SMP1_Pos (3U)
1724 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
1725 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
1726 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
1727 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
1728 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
1730 #define ADC_SMPR1_SMP2_Pos (6U)
1731 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
1732 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
1733 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
1734 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
1735 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
1737 #define ADC_SMPR1_SMP3_Pos (9U)
1738 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
1739 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
1740 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
1741 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
1742 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
1744 #define ADC_SMPR1_SMP4_Pos (12U)
1745 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
1746 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
1747 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
1748 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
1749 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
1751 #define ADC_SMPR1_SMP5_Pos (15U)
1752 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
1753 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
1754 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
1755 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
1756 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
1758 #define ADC_SMPR1_SMP6_Pos (18U)
1759 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
1760 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
1761 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
1762 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
1763 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
1765 #define ADC_SMPR1_SMP7_Pos (21U)
1766 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
1767 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
1768 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
1769 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
1770 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
1772 #define ADC_SMPR1_SMP8_Pos (24U)
1773 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
1774 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
1775 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
1776 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
1777 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
1779 #define ADC_SMPR1_SMP9_Pos (27U)
1780 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
1781 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
1782 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
1783 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
1784 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
1786 /******************** Bit definition for ADC_SMPR2 register *****************/
1787 #define ADC_SMPR2_SMP10_Pos (0U)
1788 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
1789 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
1790 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
1791 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
1792 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
1794 #define ADC_SMPR2_SMP11_Pos (3U)
1795 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
1796 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
1797 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
1798 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
1799 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
1801 #define ADC_SMPR2_SMP12_Pos (6U)
1802 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
1803 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
1804 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
1805 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
1806 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
1808 #define ADC_SMPR2_SMP13_Pos (9U)
1809 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
1810 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
1811 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
1812 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
1813 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
1815 #define ADC_SMPR2_SMP14_Pos (12U)
1816 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
1817 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
1818 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
1819 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
1820 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
1822 #define ADC_SMPR2_SMP15_Pos (15U)
1823 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
1824 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
1825 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
1826 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
1827 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
1829 #define ADC_SMPR2_SMP16_Pos (18U)
1830 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
1831 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
1832 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
1833 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
1834 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
1836 #define ADC_SMPR2_SMP17_Pos (21U)
1837 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
1838 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
1839 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
1840 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
1841 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
1843 #define ADC_SMPR2_SMP18_Pos (24U)
1844 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
1845 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
1846 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
1847 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
1848 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
1850 /******************** Bit definition for ADC_TR1 register *******************/
1851 #define ADC_TR1_LT1_Pos (0U)
1852 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)
1853 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk
1854 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)
1855 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)
1856 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)
1857 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)
1858 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)
1859 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)
1860 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)
1861 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)
1862 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)
1863 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)
1864 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)
1865 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)
1867 #define ADC_TR1_HT1_Pos (16U)
1868 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)
1869 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk
1870 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)
1871 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)
1872 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)
1873 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)
1874 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)
1875 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)
1876 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)
1877 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)
1878 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)
1879 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)
1880 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)
1881 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)
1883 /******************** Bit definition for ADC_TR2 register *******************/
1884 #define ADC_TR2_LT2_Pos (0U)
1885 #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)
1886 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk
1887 #define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos)
1888 #define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos)
1889 #define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos)
1890 #define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos)
1891 #define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos)
1892 #define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos)
1893 #define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos)
1894 #define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos)
1896 #define ADC_TR2_HT2_Pos (16U)
1897 #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)
1898 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk
1899 #define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos)
1900 #define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos)
1901 #define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos)
1902 #define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos)
1903 #define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos)
1904 #define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos)
1905 #define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos)
1906 #define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos)
1908 /******************** Bit definition for ADC_TR3 register *******************/
1909 #define ADC_TR3_LT3_Pos (0U)
1910 #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)
1911 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk
1912 #define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos)
1913 #define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos)
1914 #define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos)
1915 #define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos)
1916 #define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos)
1917 #define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos)
1918 #define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos)
1919 #define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos)
1921 #define ADC_TR3_HT3_Pos (16U)
1922 #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)
1923 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk
1924 #define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos)
1925 #define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos)
1926 #define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos)
1927 #define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos)
1928 #define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos)
1929 #define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos)
1930 #define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos)
1931 #define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos)
1933 /******************** Bit definition for ADC_SQR1 register ******************/
1934 #define ADC_SQR1_L_Pos (0U)
1935 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1936 #define ADC_SQR1_L ADC_SQR1_L_Msk
1937 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1938 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1939 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1940 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1942 #define ADC_SQR1_SQ1_Pos (6U)
1943 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
1944 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
1945 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
1946 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
1947 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
1948 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
1949 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
1951 #define ADC_SQR1_SQ2_Pos (12U)
1952 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
1953 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
1954 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
1955 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
1956 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
1957 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
1958 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
1960 #define ADC_SQR1_SQ3_Pos (18U)
1961 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
1962 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
1963 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
1964 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
1965 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
1966 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
1967 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
1969 #define ADC_SQR1_SQ4_Pos (24U)
1970 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
1971 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
1972 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
1973 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
1974 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
1975 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
1976 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
1978 /******************** Bit definition for ADC_SQR2 register ******************/
1979 #define ADC_SQR2_SQ5_Pos (0U)
1980 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
1981 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
1982 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
1983 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
1984 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
1985 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
1986 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
1988 #define ADC_SQR2_SQ6_Pos (6U)
1989 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
1990 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
1991 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
1992 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
1993 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
1994 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
1995 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
1997 #define ADC_SQR2_SQ7_Pos (12U)
1998 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1999 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
2000 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
2001 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
2002 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
2003 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
2004 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
2006 #define ADC_SQR2_SQ8_Pos (18U)
2007 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
2008 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
2009 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
2010 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
2011 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
2012 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
2013 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
2015 #define ADC_SQR2_SQ9_Pos (24U)
2016 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
2017 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
2018 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
2019 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
2020 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
2021 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
2022 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
2024 /******************** Bit definition for ADC_SQR3 register ******************/
2025 #define ADC_SQR3_SQ10_Pos (0U)
2026 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
2027 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
2028 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
2029 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
2030 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
2031 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
2032 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
2034 #define ADC_SQR3_SQ11_Pos (6U)
2035 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
2036 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
2037 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
2038 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
2039 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
2040 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
2041 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
2043 #define ADC_SQR3_SQ12_Pos (12U)
2044 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
2045 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
2046 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
2047 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
2048 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
2049 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
2050 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
2052 #define ADC_SQR3_SQ13_Pos (18U)
2053 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
2054 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
2055 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
2056 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
2057 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
2058 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
2059 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
2061 #define ADC_SQR3_SQ14_Pos (24U)
2062 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
2063 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
2064 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
2065 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
2066 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
2067 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
2068 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
2070 /******************** Bit definition for ADC_SQR4 register ******************/
2071 #define ADC_SQR4_SQ15_Pos (0U)
2072 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
2073 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
2074 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
2075 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
2076 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
2077 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
2078 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
2080 #define ADC_SQR4_SQ16_Pos (6U)
2081 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
2082 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
2083 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
2084 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
2085 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
2086 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
2087 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
2089 /******************** Bit definition for ADC_DR register ********************/
2090 #define ADC_DR_RDATA_Pos (0U)
2091 #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)
2092 #define ADC_DR_RDATA ADC_DR_RDATA_Msk
2093 #define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos)
2094 #define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos)
2095 #define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos)
2096 #define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos)
2097 #define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos)
2098 #define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos)
2099 #define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos)
2100 #define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos)
2101 #define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos)
2102 #define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos)
2103 #define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos)
2104 #define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos)
2105 #define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos)
2106 #define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos)
2107 #define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos)
2108 #define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos)
2110 /******************** Bit definition for ADC_JSQR register ******************/
2111 #define ADC_JSQR_JL_Pos (0U)
2112 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
2113 #define ADC_JSQR_JL ADC_JSQR_JL_Msk
2114 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
2115 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
2117 #define ADC_JSQR_JEXTSEL_Pos (2U)
2118 #define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos)
2119 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
2120 #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)
2121 #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)
2122 #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)
2123 #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)
2125 #define ADC_JSQR_JEXTEN_Pos (6U)
2126 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
2127 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
2128 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
2129 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
2131 #define ADC_JSQR_JSQ1_Pos (8U)
2132 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
2133 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
2134 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
2135 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
2136 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
2137 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
2138 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
2140 #define ADC_JSQR_JSQ2_Pos (14U)
2141 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
2142 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
2143 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
2144 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
2145 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
2146 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
2147 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
2149 #define ADC_JSQR_JSQ3_Pos (20U)
2150 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
2151 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
2152 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
2153 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
2154 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
2155 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
2156 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
2158 #define ADC_JSQR_JSQ4_Pos (26U)
2159 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
2160 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
2161 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
2162 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
2163 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
2164 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
2165 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
2167 /******************** Bit definition for ADC_OFR1 register ******************/
2168 #define ADC_OFR1_OFFSET1_Pos (0U)
2169 #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)
2170 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
2171 #define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos)
2172 #define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos)
2173 #define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos)
2174 #define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos)
2175 #define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos)
2176 #define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos)
2177 #define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos)
2178 #define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos)
2179 #define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos)
2180 #define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos)
2181 #define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos)
2182 #define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos)
2184 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
2185 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
2186 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
2187 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
2188 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
2189 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
2190 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
2191 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
2193 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
2194 #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)
2195 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk
2197 /******************** Bit definition for ADC_OFR2 register ******************/
2198 #define ADC_OFR2_OFFSET2_Pos (0U)
2199 #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)
2200 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
2201 #define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos)
2202 #define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos)
2203 #define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos)
2204 #define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos)
2205 #define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos)
2206 #define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos)
2207 #define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos)
2208 #define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos)
2209 #define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos)
2210 #define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos)
2211 #define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos)
2212 #define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos)
2214 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
2215 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
2216 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
2217 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
2218 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
2219 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
2220 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
2221 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
2223 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
2224 #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)
2225 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk
2227 /******************** Bit definition for ADC_OFR3 register ******************/
2228 #define ADC_OFR3_OFFSET3_Pos (0U)
2229 #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)
2230 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
2231 #define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos)
2232 #define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos)
2233 #define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos)
2234 #define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos)
2235 #define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos)
2236 #define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos)
2237 #define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos)
2238 #define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos)
2239 #define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos)
2240 #define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos)
2241 #define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos)
2242 #define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos)
2244 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
2245 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
2246 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
2247 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
2248 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
2249 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
2250 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
2251 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
2253 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
2254 #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)
2255 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk
2257 /******************** Bit definition for ADC_OFR4 register ******************/
2258 #define ADC_OFR4_OFFSET4_Pos (0U)
2259 #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)
2260 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
2261 #define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos)
2262 #define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos)
2263 #define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos)
2264 #define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos)
2265 #define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos)
2266 #define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos)
2267 #define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos)
2268 #define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos)
2269 #define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos)
2270 #define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos)
2271 #define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos)
2272 #define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos)
2274 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
2275 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
2276 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
2277 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
2278 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
2279 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
2280 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
2281 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
2283 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
2284 #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)
2285 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk
2287 /******************** Bit definition for ADC_JDR1 register ******************/
2288 #define ADC_JDR1_JDATA_Pos (0U)
2289 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
2290 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
2291 #define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos)
2292 #define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos)
2293 #define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos)
2294 #define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos)
2295 #define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos)
2296 #define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos)
2297 #define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos)
2298 #define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos)
2299 #define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos)
2300 #define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos)
2301 #define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos)
2302 #define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos)
2303 #define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos)
2304 #define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos)
2305 #define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos)
2306 #define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos)
2308 /******************** Bit definition for ADC_JDR2 register ******************/
2309 #define ADC_JDR2_JDATA_Pos (0U)
2310 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
2311 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
2312 #define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos)
2313 #define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos)
2314 #define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos)
2315 #define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos)
2316 #define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos)
2317 #define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos)
2318 #define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos)
2319 #define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos)
2320 #define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos)
2321 #define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos)
2322 #define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos)
2323 #define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos)
2324 #define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos)
2325 #define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos)
2326 #define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos)
2327 #define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos)
2329 /******************** Bit definition for ADC_JDR3 register ******************/
2330 #define ADC_JDR3_JDATA_Pos (0U)
2331 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
2332 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
2333 #define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos)
2334 #define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos)
2335 #define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos)
2336 #define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos)
2337 #define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos)
2338 #define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos)
2339 #define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos)
2340 #define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos)
2341 #define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos)
2342 #define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos)
2343 #define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos)
2344 #define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos)
2345 #define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos)
2346 #define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos)
2347 #define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos)
2348 #define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos)
2350 /******************** Bit definition for ADC_JDR4 register ******************/
2351 #define ADC_JDR4_JDATA_Pos (0U)
2352 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
2353 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
2354 #define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos)
2355 #define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos)
2356 #define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos)
2357 #define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos)
2358 #define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos)
2359 #define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos)
2360 #define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos)
2361 #define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos)
2362 #define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos)
2363 #define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos)
2364 #define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos)
2365 #define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos)
2366 #define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos)
2367 #define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos)
2368 #define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos)
2369 #define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos)
2371 /******************** Bit definition for ADC_AWD2CR register ****************/
2372 #define ADC_AWD2CR_AWD2CH_Pos (0U)
2373 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)
2374 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
2375 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
2376 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
2377 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
2378 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
2379 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
2380 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
2381 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
2382 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
2383 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
2384 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
2385 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
2386 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
2387 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
2388 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
2389 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
2390 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
2391 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
2392 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
2393 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
2395 /******************** Bit definition for ADC_AWD3CR register ****************/
2396 #define ADC_AWD3CR_AWD3CH_Pos (0U)
2397 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)
2398 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
2399 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
2400 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
2401 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
2402 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
2403 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
2404 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
2405 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
2406 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
2407 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
2408 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
2409 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
2410 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
2411 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
2412 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
2413 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
2414 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
2415 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
2416 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
2417 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
2419 /******************** Bit definition for ADC_DIFSEL register ****************/
2420 #define ADC_DIFSEL_DIFSEL_Pos (0U)
2421 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)
2422 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
2423 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
2424 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
2425 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
2426 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
2427 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
2428 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
2429 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
2430 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
2431 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
2432 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
2433 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
2434 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
2435 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
2436 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
2437 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
2438 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
2439 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
2440 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
2441 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
2443 /******************** Bit definition for ADC_CALFACT register ***************/
2444 #define ADC_CALFACT_CALFACT_S_Pos (0U)
2445 #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)
2446 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
2447 #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)
2448 #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)
2449 #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)
2450 #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)
2451 #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)
2452 #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)
2453 #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)
2455 #define ADC_CALFACT_CALFACT_D_Pos (16U)
2456 #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)
2457 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
2458 #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)
2459 #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)
2460 #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)
2461 #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)
2462 #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)
2463 #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)
2464 #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)
2466 /************************* ADC Common registers *****************************/
2467 /******************** Bit definition for ADC_CSR register *******************/
2468 #define ADC_CSR_ADRDY_MST_Pos (0U)
2469 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
2470 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
2471 #define ADC_CSR_EOSMP_MST_Pos (1U)
2472 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
2473 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
2474 #define ADC_CSR_EOC_MST_Pos (2U)
2475 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
2476 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
2477 #define ADC_CSR_EOS_MST_Pos (3U)
2478 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
2479 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
2480 #define ADC_CSR_OVR_MST_Pos (4U)
2481 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
2482 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
2483 #define ADC_CSR_JEOC_MST_Pos (5U)
2484 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
2485 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
2486 #define ADC_CSR_JEOS_MST_Pos (6U)
2487 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
2488 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
2489 #define ADC_CSR_AWD1_MST_Pos (7U)
2490 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
2491 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
2492 #define ADC_CSR_AWD2_MST_Pos (8U)
2493 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
2494 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
2495 #define ADC_CSR_AWD3_MST_Pos (9U)
2496 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
2497 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
2498 #define ADC_CSR_JQOVF_MST_Pos (10U)
2499 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
2500 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
2502 #define ADC_CSR_ADRDY_SLV_Pos (16U)
2503 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
2504 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
2505 #define ADC_CSR_EOSMP_SLV_Pos (17U)
2506 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
2507 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
2508 #define ADC_CSR_EOC_SLV_Pos (18U)
2509 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
2510 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
2511 #define ADC_CSR_EOS_SLV_Pos (19U)
2512 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
2513 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
2514 #define ADC_CSR_OVR_SLV_Pos (20U)
2515 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
2516 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
2517 #define ADC_CSR_JEOC_SLV_Pos (21U)
2518 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
2519 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
2520 #define ADC_CSR_JEOS_SLV_Pos (22U)
2521 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
2522 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
2523 #define ADC_CSR_AWD1_SLV_Pos (23U)
2524 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
2525 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
2526 #define ADC_CSR_AWD2_SLV_Pos (24U)
2527 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
2528 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
2529 #define ADC_CSR_AWD3_SLV_Pos (25U)
2530 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
2531 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
2532 #define ADC_CSR_JQOVF_SLV_Pos (26U)
2533 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
2534 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
2536 /******************** Bit definition for ADC_CCR register *******************/
2537 #define ADC_CCR_DUAL_Pos (0U)
2538 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
2539 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
2540 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
2541 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
2542 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
2543 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
2544 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
2546 #define ADC_CCR_DELAY_Pos (8U)
2547 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
2548 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
2549 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
2550 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
2551 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
2552 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
2554 #define ADC_CCR_DMACFG_Pos (13U)
2555 #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)
2556 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk
2558 #define ADC_CCR_MDMA_Pos (14U)
2559 #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)
2560 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk
2561 #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)
2562 #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)
2564 #define ADC_CCR_CKMODE_Pos (16U)
2565 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
2566 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
2567 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
2568 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
2570 #define ADC_CCR_PRESC_Pos (18U)
2571 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
2572 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
2573 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
2574 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
2575 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
2576 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
2578 #define ADC_CCR_VREFEN_Pos (22U)
2579 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
2580 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
2581 #define ADC_CCR_TSEN_Pos (23U)
2582 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
2583 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
2584 #define ADC_CCR_VBATEN_Pos (24U)
2585 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
2586 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
2588 /******************** Bit definition for ADC_CDR register *******************/
2589 #define ADC_CDR_RDATA_MST_Pos (0U)
2590 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
2591 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
2592 #define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos)
2593 #define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos)
2594 #define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos)
2595 #define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos)
2596 #define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos)
2597 #define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos)
2598 #define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos)
2599 #define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos)
2600 #define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos)
2601 #define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos)
2602 #define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos)
2603 #define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos)
2604 #define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos)
2605 #define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos)
2606 #define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos)
2607 #define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos)
2609 #define ADC_CDR_RDATA_SLV_Pos (16U)
2610 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
2611 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
2612 #define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos)
2613 #define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos)
2614 #define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos)
2615 #define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos)
2616 #define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos)
2617 #define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos)
2618 #define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos)
2619 #define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos)
2620 #define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos)
2621 #define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos)
2622 #define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos)
2623 #define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos)
2624 #define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos)
2625 #define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos)
2626 #define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos)
2627 #define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos)
2629 /******************************************************************************/
2630 /* */
2631 /* Controller Area Network */
2632 /* */
2633 /******************************************************************************/
2635 /******************* Bit definition for CAN_MCR register ********************/
2636 #define CAN_MCR_INRQ_Pos (0U)
2637 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2638 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2639 #define CAN_MCR_SLEEP_Pos (1U)
2640 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2641 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2642 #define CAN_MCR_TXFP_Pos (2U)
2643 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2644 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2645 #define CAN_MCR_RFLM_Pos (3U)
2646 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2647 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2648 #define CAN_MCR_NART_Pos (4U)
2649 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2650 #define CAN_MCR_NART CAN_MCR_NART_Msk
2651 #define CAN_MCR_AWUM_Pos (5U)
2652 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2653 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2654 #define CAN_MCR_ABOM_Pos (6U)
2655 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2656 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2657 #define CAN_MCR_TTCM_Pos (7U)
2658 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2659 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2660 #define CAN_MCR_RESET_Pos (15U)
2661 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2662 #define CAN_MCR_RESET CAN_MCR_RESET_Msk
2664 /******************* Bit definition for CAN_MSR register ********************/
2665 #define CAN_MSR_INAK_Pos (0U)
2666 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2667 #define CAN_MSR_INAK CAN_MSR_INAK_Msk
2668 #define CAN_MSR_SLAK_Pos (1U)
2669 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2670 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2671 #define CAN_MSR_ERRI_Pos (2U)
2672 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2673 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2674 #define CAN_MSR_WKUI_Pos (3U)
2675 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2676 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2677 #define CAN_MSR_SLAKI_Pos (4U)
2678 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2679 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2680 #define CAN_MSR_TXM_Pos (8U)
2681 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2682 #define CAN_MSR_TXM CAN_MSR_TXM_Msk
2683 #define CAN_MSR_RXM_Pos (9U)
2684 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2685 #define CAN_MSR_RXM CAN_MSR_RXM_Msk
2686 #define CAN_MSR_SAMP_Pos (10U)
2687 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2688 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2689 #define CAN_MSR_RX_Pos (11U)
2690 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2691 #define CAN_MSR_RX CAN_MSR_RX_Msk
2693 /******************* Bit definition for CAN_TSR register ********************/
2694 #define CAN_TSR_RQCP0_Pos (0U)
2695 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2696 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2697 #define CAN_TSR_TXOK0_Pos (1U)
2698 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2699 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2700 #define CAN_TSR_ALST0_Pos (2U)
2701 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2702 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2703 #define CAN_TSR_TERR0_Pos (3U)
2704 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2705 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2706 #define CAN_TSR_ABRQ0_Pos (7U)
2707 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2708 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2709 #define CAN_TSR_RQCP1_Pos (8U)
2710 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2711 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2712 #define CAN_TSR_TXOK1_Pos (9U)
2713 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2714 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2715 #define CAN_TSR_ALST1_Pos (10U)
2716 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2717 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2718 #define CAN_TSR_TERR1_Pos (11U)
2719 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2720 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2721 #define CAN_TSR_ABRQ1_Pos (15U)
2722 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2723 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2724 #define CAN_TSR_RQCP2_Pos (16U)
2725 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2726 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2727 #define CAN_TSR_TXOK2_Pos (17U)
2728 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2729 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2730 #define CAN_TSR_ALST2_Pos (18U)
2731 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2732 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2733 #define CAN_TSR_TERR2_Pos (19U)
2734 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2735 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2736 #define CAN_TSR_ABRQ2_Pos (23U)
2737 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2738 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2739 #define CAN_TSR_CODE_Pos (24U)
2740 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2741 #define CAN_TSR_CODE CAN_TSR_CODE_Msk
2743 #define CAN_TSR_TME_Pos (26U)
2744 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2745 #define CAN_TSR_TME CAN_TSR_TME_Msk
2746 #define CAN_TSR_TME0_Pos (26U)
2747 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2748 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2749 #define CAN_TSR_TME1_Pos (27U)
2750 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2751 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2752 #define CAN_TSR_TME2_Pos (28U)
2753 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2754 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2756 #define CAN_TSR_LOW_Pos (29U)
2757 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2758 #define CAN_TSR_LOW CAN_TSR_LOW_Msk
2759 #define CAN_TSR_LOW0_Pos (29U)
2760 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2761 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2762 #define CAN_TSR_LOW1_Pos (30U)
2763 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2764 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2765 #define CAN_TSR_LOW2_Pos (31U)
2766 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2767 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2769 /******************* Bit definition for CAN_RF0R register *******************/
2770 #define CAN_RF0R_FMP0_Pos (0U)
2771 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2772 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2773 #define CAN_RF0R_FULL0_Pos (3U)
2774 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2775 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2776 #define CAN_RF0R_FOVR0_Pos (4U)
2777 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2778 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2779 #define CAN_RF0R_RFOM0_Pos (5U)
2780 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2781 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2783 /******************* Bit definition for CAN_RF1R register *******************/
2784 #define CAN_RF1R_FMP1_Pos (0U)
2785 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2786 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2787 #define CAN_RF1R_FULL1_Pos (3U)
2788 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2789 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2790 #define CAN_RF1R_FOVR1_Pos (4U)
2791 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2792 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2793 #define CAN_RF1R_RFOM1_Pos (5U)
2794 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2795 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2797 /******************** Bit definition for CAN_IER register *******************/
2798 #define CAN_IER_TMEIE_Pos (0U)
2799 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2800 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2801 #define CAN_IER_FMPIE0_Pos (1U)
2802 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2803 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2804 #define CAN_IER_FFIE0_Pos (2U)
2805 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2806 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2807 #define CAN_IER_FOVIE0_Pos (3U)
2808 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2809 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2810 #define CAN_IER_FMPIE1_Pos (4U)
2811 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2812 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2813 #define CAN_IER_FFIE1_Pos (5U)
2814 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2815 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2816 #define CAN_IER_FOVIE1_Pos (6U)
2817 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2818 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2819 #define CAN_IER_EWGIE_Pos (8U)
2820 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2821 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2822 #define CAN_IER_EPVIE_Pos (9U)
2823 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2824 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2825 #define CAN_IER_BOFIE_Pos (10U)
2826 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2827 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2828 #define CAN_IER_LECIE_Pos (11U)
2829 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2830 #define CAN_IER_LECIE CAN_IER_LECIE_Msk
2831 #define CAN_IER_ERRIE_Pos (15U)
2832 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2833 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2834 #define CAN_IER_WKUIE_Pos (16U)
2835 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2836 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2837 #define CAN_IER_SLKIE_Pos (17U)
2838 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2839 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2841 /******************** Bit definition for CAN_ESR register *******************/
2842 #define CAN_ESR_EWGF_Pos (0U)
2843 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2844 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2845 #define CAN_ESR_EPVF_Pos (1U)
2846 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2847 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2848 #define CAN_ESR_BOFF_Pos (2U)
2849 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2850 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2852 #define CAN_ESR_LEC_Pos (4U)
2853 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2854 #define CAN_ESR_LEC CAN_ESR_LEC_Msk
2855 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2856 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2857 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2859 #define CAN_ESR_TEC_Pos (16U)
2860 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2861 #define CAN_ESR_TEC CAN_ESR_TEC_Msk
2862 #define CAN_ESR_REC_Pos (24U)
2863 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2864 #define CAN_ESR_REC CAN_ESR_REC_Msk
2866 /******************* Bit definition for CAN_BTR register ********************/
2867 #define CAN_BTR_BRP_Pos (0U)
2868 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2869 #define CAN_BTR_BRP CAN_BTR_BRP_Msk
2870 #define CAN_BTR_TS1_Pos (16U)
2871 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2872 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2873 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2874 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2875 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2876 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2877 #define CAN_BTR_TS2_Pos (20U)
2878 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2879 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2880 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2881 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2882 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2883 #define CAN_BTR_SJW_Pos (24U)
2884 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2885 #define CAN_BTR_SJW CAN_BTR_SJW_Msk
2886 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2887 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2888 #define CAN_BTR_LBKM_Pos (30U)
2889 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2890 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2891 #define CAN_BTR_SILM_Pos (31U)
2892 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2893 #define CAN_BTR_SILM CAN_BTR_SILM_Msk
2896 /****************** Bit definition for CAN_TI0R register ********************/
2897 #define CAN_TI0R_TXRQ_Pos (0U)
2898 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2899 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2900 #define CAN_TI0R_RTR_Pos (1U)
2901 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2902 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2903 #define CAN_TI0R_IDE_Pos (2U)
2904 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2905 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2906 #define CAN_TI0R_EXID_Pos (3U)
2907 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2908 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2909 #define CAN_TI0R_STID_Pos (21U)
2910 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2911 #define CAN_TI0R_STID CAN_TI0R_STID_Msk
2913 /****************** Bit definition for CAN_TDT0R register *******************/
2914 #define CAN_TDT0R_DLC_Pos (0U)
2915 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2916 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2917 #define CAN_TDT0R_TGT_Pos (8U)
2918 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2919 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2920 #define CAN_TDT0R_TIME_Pos (16U)
2921 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2922 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2924 /****************** Bit definition for CAN_TDL0R register *******************/
2925 #define CAN_TDL0R_DATA0_Pos (0U)
2926 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2927 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2928 #define CAN_TDL0R_DATA1_Pos (8U)
2929 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2930 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2931 #define CAN_TDL0R_DATA2_Pos (16U)
2932 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2933 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2934 #define CAN_TDL0R_DATA3_Pos (24U)
2935 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2936 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2938 /****************** Bit definition for CAN_TDH0R register *******************/
2939 #define CAN_TDH0R_DATA4_Pos (0U)
2940 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2941 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2942 #define CAN_TDH0R_DATA5_Pos (8U)
2943 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2944 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2945 #define CAN_TDH0R_DATA6_Pos (16U)
2946 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2947 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2948 #define CAN_TDH0R_DATA7_Pos (24U)
2949 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2950 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2952 /******************* Bit definition for CAN_TI1R register *******************/
2953 #define CAN_TI1R_TXRQ_Pos (0U)
2954 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2955 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2956 #define CAN_TI1R_RTR_Pos (1U)
2957 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2958 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2959 #define CAN_TI1R_IDE_Pos (2U)
2960 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2961 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2962 #define CAN_TI1R_EXID_Pos (3U)
2963 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2964 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2965 #define CAN_TI1R_STID_Pos (21U)
2966 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2967 #define CAN_TI1R_STID CAN_TI1R_STID_Msk
2969 /******************* Bit definition for CAN_TDT1R register ******************/
2970 #define CAN_TDT1R_DLC_Pos (0U)
2971 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2972 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2973 #define CAN_TDT1R_TGT_Pos (8U)
2974 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2975 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2976 #define CAN_TDT1R_TIME_Pos (16U)
2977 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2978 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2980 /******************* Bit definition for CAN_TDL1R register ******************/
2981 #define CAN_TDL1R_DATA0_Pos (0U)
2982 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2983 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2984 #define CAN_TDL1R_DATA1_Pos (8U)
2985 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2986 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2987 #define CAN_TDL1R_DATA2_Pos (16U)
2988 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2989 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2990 #define CAN_TDL1R_DATA3_Pos (24U)
2991 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2992 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2994 /******************* Bit definition for CAN_TDH1R register ******************/
2995 #define CAN_TDH1R_DATA4_Pos (0U)
2996 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2997 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2998 #define CAN_TDH1R_DATA5_Pos (8U)
2999 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
3000 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
3001 #define CAN_TDH1R_DATA6_Pos (16U)
3002 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
3003 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
3004 #define CAN_TDH1R_DATA7_Pos (24U)
3005 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
3006 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
3008 /******************* Bit definition for CAN_TI2R register *******************/
3009 #define CAN_TI2R_TXRQ_Pos (0U)
3010 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
3011 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
3012 #define CAN_TI2R_RTR_Pos (1U)
3013 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
3014 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
3015 #define CAN_TI2R_IDE_Pos (2U)
3016 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
3017 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
3018 #define CAN_TI2R_EXID_Pos (3U)
3019 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
3020 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
3021 #define CAN_TI2R_STID_Pos (21U)
3022 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
3023 #define CAN_TI2R_STID CAN_TI2R_STID_Msk
3025 /******************* Bit definition for CAN_TDT2R register ******************/
3026 #define CAN_TDT2R_DLC_Pos (0U)
3027 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
3028 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
3029 #define CAN_TDT2R_TGT_Pos (8U)
3030 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
3031 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
3032 #define CAN_TDT2R_TIME_Pos (16U)
3033 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
3034 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
3036 /******************* Bit definition for CAN_TDL2R register ******************/
3037 #define CAN_TDL2R_DATA0_Pos (0U)
3038 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
3039 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
3040 #define CAN_TDL2R_DATA1_Pos (8U)
3041 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
3042 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
3043 #define CAN_TDL2R_DATA2_Pos (16U)
3044 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
3045 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
3046 #define CAN_TDL2R_DATA3_Pos (24U)
3047 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
3048 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
3050 /******************* Bit definition for CAN_TDH2R register ******************/
3051 #define CAN_TDH2R_DATA4_Pos (0U)
3052 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
3053 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
3054 #define CAN_TDH2R_DATA5_Pos (8U)
3055 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
3056 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
3057 #define CAN_TDH2R_DATA6_Pos (16U)
3058 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
3059 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
3060 #define CAN_TDH2R_DATA7_Pos (24U)
3061 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
3062 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
3064 /******************* Bit definition for CAN_RI0R register *******************/
3065 #define CAN_RI0R_RTR_Pos (1U)
3066 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
3067 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
3068 #define CAN_RI0R_IDE_Pos (2U)
3069 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
3070 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
3071 #define CAN_RI0R_EXID_Pos (3U)
3072 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
3073 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
3074 #define CAN_RI0R_STID_Pos (21U)
3075 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
3076 #define CAN_RI0R_STID CAN_RI0R_STID_Msk
3078 /******************* Bit definition for CAN_RDT0R register ******************/
3079 #define CAN_RDT0R_DLC_Pos (0U)
3080 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
3081 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
3082 #define CAN_RDT0R_FMI_Pos (8U)
3083 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
3084 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
3085 #define CAN_RDT0R_TIME_Pos (16U)
3086 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
3087 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
3089 /******************* Bit definition for CAN_RDL0R register ******************/
3090 #define CAN_RDL0R_DATA0_Pos (0U)
3091 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
3092 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
3093 #define CAN_RDL0R_DATA1_Pos (8U)
3094 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
3095 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
3096 #define CAN_RDL0R_DATA2_Pos (16U)
3097 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
3098 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
3099 #define CAN_RDL0R_DATA3_Pos (24U)
3100 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
3101 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
3103 /******************* Bit definition for CAN_RDH0R register ******************/
3104 #define CAN_RDH0R_DATA4_Pos (0U)
3105 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
3106 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
3107 #define CAN_RDH0R_DATA5_Pos (8U)
3108 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
3109 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
3110 #define CAN_RDH0R_DATA6_Pos (16U)
3111 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
3112 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
3113 #define CAN_RDH0R_DATA7_Pos (24U)
3114 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
3115 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
3117 /******************* Bit definition for CAN_RI1R register *******************/
3118 #define CAN_RI1R_RTR_Pos (1U)
3119 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
3120 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
3121 #define CAN_RI1R_IDE_Pos (2U)
3122 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
3123 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
3124 #define CAN_RI1R_EXID_Pos (3U)
3125 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
3126 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
3127 #define CAN_RI1R_STID_Pos (21U)
3128 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
3129 #define CAN_RI1R_STID CAN_RI1R_STID_Msk
3131 /******************* Bit definition for CAN_RDT1R register ******************/
3132 #define CAN_RDT1R_DLC_Pos (0U)
3133 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
3134 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
3135 #define CAN_RDT1R_FMI_Pos (8U)
3136 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
3137 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
3138 #define CAN_RDT1R_TIME_Pos (16U)
3139 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
3140 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
3142 /******************* Bit definition for CAN_RDL1R register ******************/
3143 #define CAN_RDL1R_DATA0_Pos (0U)
3144 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
3145 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
3146 #define CAN_RDL1R_DATA1_Pos (8U)
3147 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
3148 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
3149 #define CAN_RDL1R_DATA2_Pos (16U)
3150 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
3151 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
3152 #define CAN_RDL1R_DATA3_Pos (24U)
3153 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
3154 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
3156 /******************* Bit definition for CAN_RDH1R register ******************/
3157 #define CAN_RDH1R_DATA4_Pos (0U)
3158 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
3159 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
3160 #define CAN_RDH1R_DATA5_Pos (8U)
3161 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
3162 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
3163 #define CAN_RDH1R_DATA6_Pos (16U)
3164 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
3165 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
3166 #define CAN_RDH1R_DATA7_Pos (24U)
3167 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
3168 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
3171 /******************* Bit definition for CAN_FMR register ********************/
3172 #define CAN_FMR_FINIT_Pos (0U)
3173 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
3174 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
3176 /******************* Bit definition for CAN_FM1R register *******************/
3177 #define CAN_FM1R_FBM_Pos (0U)
3178 #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
3179 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
3180 #define CAN_FM1R_FBM0_Pos (0U)
3181 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
3182 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
3183 #define CAN_FM1R_FBM1_Pos (1U)
3184 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
3185 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
3186 #define CAN_FM1R_FBM2_Pos (2U)
3187 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
3188 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
3189 #define CAN_FM1R_FBM3_Pos (3U)
3190 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
3191 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
3192 #define CAN_FM1R_FBM4_Pos (4U)
3193 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
3194 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
3195 #define CAN_FM1R_FBM5_Pos (5U)
3196 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
3197 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
3198 #define CAN_FM1R_FBM6_Pos (6U)
3199 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
3200 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
3201 #define CAN_FM1R_FBM7_Pos (7U)
3202 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
3203 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
3204 #define CAN_FM1R_FBM8_Pos (8U)
3205 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
3206 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
3207 #define CAN_FM1R_FBM9_Pos (9U)
3208 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
3209 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
3210 #define CAN_FM1R_FBM10_Pos (10U)
3211 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
3212 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
3213 #define CAN_FM1R_FBM11_Pos (11U)
3214 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
3215 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
3216 #define CAN_FM1R_FBM12_Pos (12U)
3217 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
3218 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
3219 #define CAN_FM1R_FBM13_Pos (13U)
3220 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
3221 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
3223 /******************* Bit definition for CAN_FS1R register *******************/
3224 #define CAN_FS1R_FSC_Pos (0U)
3225 #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
3226 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
3227 #define CAN_FS1R_FSC0_Pos (0U)
3228 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
3229 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
3230 #define CAN_FS1R_FSC1_Pos (1U)
3231 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
3232 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
3233 #define CAN_FS1R_FSC2_Pos (2U)
3234 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
3235 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
3236 #define CAN_FS1R_FSC3_Pos (3U)
3237 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
3238 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
3239 #define CAN_FS1R_FSC4_Pos (4U)
3240 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
3241 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
3242 #define CAN_FS1R_FSC5_Pos (5U)
3243 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
3244 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
3245 #define CAN_FS1R_FSC6_Pos (6U)
3246 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
3247 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
3248 #define CAN_FS1R_FSC7_Pos (7U)
3249 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
3250 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
3251 #define CAN_FS1R_FSC8_Pos (8U)
3252 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
3253 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
3254 #define CAN_FS1R_FSC9_Pos (9U)
3255 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
3256 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
3257 #define CAN_FS1R_FSC10_Pos (10U)
3258 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
3259 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
3260 #define CAN_FS1R_FSC11_Pos (11U)
3261 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
3262 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
3263 #define CAN_FS1R_FSC12_Pos (12U)
3264 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
3265 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
3266 #define CAN_FS1R_FSC13_Pos (13U)
3267 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
3268 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
3270 /****************** Bit definition for CAN_FFA1R register *******************/
3271 #define CAN_FFA1R_FFA_Pos (0U)
3272 #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
3273 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
3274 #define CAN_FFA1R_FFA0_Pos (0U)
3275 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
3276 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
3277 #define CAN_FFA1R_FFA1_Pos (1U)
3278 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
3279 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
3280 #define CAN_FFA1R_FFA2_Pos (2U)
3281 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
3282 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
3283 #define CAN_FFA1R_FFA3_Pos (3U)
3284 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
3285 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
3286 #define CAN_FFA1R_FFA4_Pos (4U)
3287 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
3288 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
3289 #define CAN_FFA1R_FFA5_Pos (5U)
3290 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
3291 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
3292 #define CAN_FFA1R_FFA6_Pos (6U)
3293 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
3294 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
3295 #define CAN_FFA1R_FFA7_Pos (7U)
3296 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
3297 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
3298 #define CAN_FFA1R_FFA8_Pos (8U)
3299 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
3300 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
3301 #define CAN_FFA1R_FFA9_Pos (9U)
3302 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
3303 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
3304 #define CAN_FFA1R_FFA10_Pos (10U)
3305 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
3306 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
3307 #define CAN_FFA1R_FFA11_Pos (11U)
3308 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
3309 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
3310 #define CAN_FFA1R_FFA12_Pos (12U)
3311 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
3312 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
3313 #define CAN_FFA1R_FFA13_Pos (13U)
3314 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
3315 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
3317 /******************* Bit definition for CAN_FA1R register *******************/
3318 #define CAN_FA1R_FACT_Pos (0U)
3319 #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
3320 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
3321 #define CAN_FA1R_FACT0_Pos (0U)
3322 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
3323 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
3324 #define CAN_FA1R_FACT1_Pos (1U)
3325 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
3326 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
3327 #define CAN_FA1R_FACT2_Pos (2U)
3328 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
3329 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
3330 #define CAN_FA1R_FACT3_Pos (3U)
3331 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
3332 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
3333 #define CAN_FA1R_FACT4_Pos (4U)
3334 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
3335 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
3336 #define CAN_FA1R_FACT5_Pos (5U)
3337 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
3338 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
3339 #define CAN_FA1R_FACT6_Pos (6U)
3340 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
3341 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
3342 #define CAN_FA1R_FACT7_Pos (7U)
3343 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
3344 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
3345 #define CAN_FA1R_FACT8_Pos (8U)
3346 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
3347 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
3348 #define CAN_FA1R_FACT9_Pos (9U)
3349 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
3350 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
3351 #define CAN_FA1R_FACT10_Pos (10U)
3352 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
3353 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
3354 #define CAN_FA1R_FACT11_Pos (11U)
3355 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
3356 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
3357 #define CAN_FA1R_FACT12_Pos (12U)
3358 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
3359 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
3360 #define CAN_FA1R_FACT13_Pos (13U)
3361 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
3362 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
3364 /******************* Bit definition for CAN_F0R1 register *******************/
3365 #define CAN_F0R1_FB0_Pos (0U)
3366 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
3367 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
3368 #define CAN_F0R1_FB1_Pos (1U)
3369 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
3370 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
3371 #define CAN_F0R1_FB2_Pos (2U)
3372 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
3373 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
3374 #define CAN_F0R1_FB3_Pos (3U)
3375 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
3376 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
3377 #define CAN_F0R1_FB4_Pos (4U)
3378 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
3379 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
3380 #define CAN_F0R1_FB5_Pos (5U)
3381 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
3382 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
3383 #define CAN_F0R1_FB6_Pos (6U)
3384 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
3385 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
3386 #define CAN_F0R1_FB7_Pos (7U)
3387 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
3388 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
3389 #define CAN_F0R1_FB8_Pos (8U)
3390 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
3391 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
3392 #define CAN_F0R1_FB9_Pos (9U)
3393 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
3394 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
3395 #define CAN_F0R1_FB10_Pos (10U)
3396 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
3397 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
3398 #define CAN_F0R1_FB11_Pos (11U)
3399 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
3400 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
3401 #define CAN_F0R1_FB12_Pos (12U)
3402 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
3403 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
3404 #define CAN_F0R1_FB13_Pos (13U)
3405 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
3406 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
3407 #define CAN_F0R1_FB14_Pos (14U)
3408 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
3409 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
3410 #define CAN_F0R1_FB15_Pos (15U)
3411 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
3412 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
3413 #define CAN_F0R1_FB16_Pos (16U)
3414 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
3415 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
3416 #define CAN_F0R1_FB17_Pos (17U)
3417 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
3418 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
3419 #define CAN_F0R1_FB18_Pos (18U)
3420 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
3421 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
3422 #define CAN_F0R1_FB19_Pos (19U)
3423 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
3424 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
3425 #define CAN_F0R1_FB20_Pos (20U)
3426 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
3427 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
3428 #define CAN_F0R1_FB21_Pos (21U)
3429 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
3430 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
3431 #define CAN_F0R1_FB22_Pos (22U)
3432 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
3433 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
3434 #define CAN_F0R1_FB23_Pos (23U)
3435 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
3436 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
3437 #define CAN_F0R1_FB24_Pos (24U)
3438 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
3439 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
3440 #define CAN_F0R1_FB25_Pos (25U)
3441 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
3442 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
3443 #define CAN_F0R1_FB26_Pos (26U)
3444 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
3445 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
3446 #define CAN_F0R1_FB27_Pos (27U)
3447 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
3448 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
3449 #define CAN_F0R1_FB28_Pos (28U)
3450 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
3451 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
3452 #define CAN_F0R1_FB29_Pos (29U)
3453 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
3454 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
3455 #define CAN_F0R1_FB30_Pos (30U)
3456 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
3457 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
3458 #define CAN_F0R1_FB31_Pos (31U)
3459 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
3460 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3462 /******************* Bit definition for CAN_F1R1 register *******************/
3463 #define CAN_F1R1_FB0_Pos (0U)
3464 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3465 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3466 #define CAN_F1R1_FB1_Pos (1U)
3467 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3468 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3469 #define CAN_F1R1_FB2_Pos (2U)
3470 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3471 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3472 #define CAN_F1R1_FB3_Pos (3U)
3473 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3474 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3475 #define CAN_F1R1_FB4_Pos (4U)
3476 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3477 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3478 #define CAN_F1R1_FB5_Pos (5U)
3479 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3480 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3481 #define CAN_F1R1_FB6_Pos (6U)
3482 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3483 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3484 #define CAN_F1R1_FB7_Pos (7U)
3485 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3486 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3487 #define CAN_F1R1_FB8_Pos (8U)
3488 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3489 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3490 #define CAN_F1R1_FB9_Pos (9U)
3491 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3492 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3493 #define CAN_F1R1_FB10_Pos (10U)
3494 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3495 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3496 #define CAN_F1R1_FB11_Pos (11U)
3497 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3498 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3499 #define CAN_F1R1_FB12_Pos (12U)
3500 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3501 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3502 #define CAN_F1R1_FB13_Pos (13U)
3503 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3504 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3505 #define CAN_F1R1_FB14_Pos (14U)
3506 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3507 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3508 #define CAN_F1R1_FB15_Pos (15U)
3509 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3510 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3511 #define CAN_F1R1_FB16_Pos (16U)
3512 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3513 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3514 #define CAN_F1R1_FB17_Pos (17U)
3515 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3516 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3517 #define CAN_F1R1_FB18_Pos (18U)
3518 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3519 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3520 #define CAN_F1R1_FB19_Pos (19U)
3521 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3522 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3523 #define CAN_F1R1_FB20_Pos (20U)
3524 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3525 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3526 #define CAN_F1R1_FB21_Pos (21U)
3527 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3528 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3529 #define CAN_F1R1_FB22_Pos (22U)
3530 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3531 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3532 #define CAN_F1R1_FB23_Pos (23U)
3533 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3534 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3535 #define CAN_F1R1_FB24_Pos (24U)
3536 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3537 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3538 #define CAN_F1R1_FB25_Pos (25U)
3539 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3540 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3541 #define CAN_F1R1_FB26_Pos (26U)
3542 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3543 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3544 #define CAN_F1R1_FB27_Pos (27U)
3545 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3546 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3547 #define CAN_F1R1_FB28_Pos (28U)
3548 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3549 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3550 #define CAN_F1R1_FB29_Pos (29U)
3551 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3552 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3553 #define CAN_F1R1_FB30_Pos (30U)
3554 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3555 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3556 #define CAN_F1R1_FB31_Pos (31U)
3557 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3558 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3560 /******************* Bit definition for CAN_F2R1 register *******************/
3561 #define CAN_F2R1_FB0_Pos (0U)
3562 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3563 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3564 #define CAN_F2R1_FB1_Pos (1U)
3565 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3566 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3567 #define CAN_F2R1_FB2_Pos (2U)
3568 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3569 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3570 #define CAN_F2R1_FB3_Pos (3U)
3571 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3572 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3573 #define CAN_F2R1_FB4_Pos (4U)
3574 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3575 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3576 #define CAN_F2R1_FB5_Pos (5U)
3577 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3578 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3579 #define CAN_F2R1_FB6_Pos (6U)
3580 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3581 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3582 #define CAN_F2R1_FB7_Pos (7U)
3583 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3584 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3585 #define CAN_F2R1_FB8_Pos (8U)
3586 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3587 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3588 #define CAN_F2R1_FB9_Pos (9U)
3589 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3590 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3591 #define CAN_F2R1_FB10_Pos (10U)
3592 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3593 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3594 #define CAN_F2R1_FB11_Pos (11U)
3595 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3596 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3597 #define CAN_F2R1_FB12_Pos (12U)
3598 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3599 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3600 #define CAN_F2R1_FB13_Pos (13U)
3601 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3602 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3603 #define CAN_F2R1_FB14_Pos (14U)
3604 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3605 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3606 #define CAN_F2R1_FB15_Pos (15U)
3607 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3608 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3609 #define CAN_F2R1_FB16_Pos (16U)
3610 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3611 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3612 #define CAN_F2R1_FB17_Pos (17U)
3613 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3614 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3615 #define CAN_F2R1_FB18_Pos (18U)
3616 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3617 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3618 #define CAN_F2R1_FB19_Pos (19U)
3619 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3620 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3621 #define CAN_F2R1_FB20_Pos (20U)
3622 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3623 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3624 #define CAN_F2R1_FB21_Pos (21U)
3625 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3626 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3627 #define CAN_F2R1_FB22_Pos (22U)
3628 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3629 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3630 #define CAN_F2R1_FB23_Pos (23U)
3631 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3632 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3633 #define CAN_F2R1_FB24_Pos (24U)
3634 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3635 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3636 #define CAN_F2R1_FB25_Pos (25U)
3637 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3638 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3639 #define CAN_F2R1_FB26_Pos (26U)
3640 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3641 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3642 #define CAN_F2R1_FB27_Pos (27U)
3643 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3644 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3645 #define CAN_F2R1_FB28_Pos (28U)
3646 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3647 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3648 #define CAN_F2R1_FB29_Pos (29U)
3649 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3650 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3651 #define CAN_F2R1_FB30_Pos (30U)
3652 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3653 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3654 #define CAN_F2R1_FB31_Pos (31U)
3655 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3656 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3658 /******************* Bit definition for CAN_F3R1 register *******************/
3659 #define CAN_F3R1_FB0_Pos (0U)
3660 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3661 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3662 #define CAN_F3R1_FB1_Pos (1U)
3663 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3664 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3665 #define CAN_F3R1_FB2_Pos (2U)
3666 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3667 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3668 #define CAN_F3R1_FB3_Pos (3U)
3669 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3670 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3671 #define CAN_F3R1_FB4_Pos (4U)
3672 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3673 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3674 #define CAN_F3R1_FB5_Pos (5U)
3675 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3676 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3677 #define CAN_F3R1_FB6_Pos (6U)
3678 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3679 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3680 #define CAN_F3R1_FB7_Pos (7U)
3681 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3682 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3683 #define CAN_F3R1_FB8_Pos (8U)
3684 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3685 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3686 #define CAN_F3R1_FB9_Pos (9U)
3687 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3688 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3689 #define CAN_F3R1_FB10_Pos (10U)
3690 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3691 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3692 #define CAN_F3R1_FB11_Pos (11U)
3693 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3694 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3695 #define CAN_F3R1_FB12_Pos (12U)
3696 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3697 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3698 #define CAN_F3R1_FB13_Pos (13U)
3699 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3700 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3701 #define CAN_F3R1_FB14_Pos (14U)
3702 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3703 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3704 #define CAN_F3R1_FB15_Pos (15U)
3705 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3706 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3707 #define CAN_F3R1_FB16_Pos (16U)
3708 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3709 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3710 #define CAN_F3R1_FB17_Pos (17U)
3711 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3712 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3713 #define CAN_F3R1_FB18_Pos (18U)
3714 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3715 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3716 #define CAN_F3R1_FB19_Pos (19U)
3717 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3718 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3719 #define CAN_F3R1_FB20_Pos (20U)
3720 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3721 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3722 #define CAN_F3R1_FB21_Pos (21U)
3723 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3724 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3725 #define CAN_F3R1_FB22_Pos (22U)
3726 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3727 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3728 #define CAN_F3R1_FB23_Pos (23U)
3729 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3730 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3731 #define CAN_F3R1_FB24_Pos (24U)
3732 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3733 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3734 #define CAN_F3R1_FB25_Pos (25U)
3735 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3736 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3737 #define CAN_F3R1_FB26_Pos (26U)
3738 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3739 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3740 #define CAN_F3R1_FB27_Pos (27U)
3741 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3742 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3743 #define CAN_F3R1_FB28_Pos (28U)
3744 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3745 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3746 #define CAN_F3R1_FB29_Pos (29U)
3747 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3748 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3749 #define CAN_F3R1_FB30_Pos (30U)
3750 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3751 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3752 #define CAN_F3R1_FB31_Pos (31U)
3753 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3754 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3756 /******************* Bit definition for CAN_F4R1 register *******************/
3757 #define CAN_F4R1_FB0_Pos (0U)
3758 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3759 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3760 #define CAN_F4R1_FB1_Pos (1U)
3761 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3762 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3763 #define CAN_F4R1_FB2_Pos (2U)
3764 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3765 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3766 #define CAN_F4R1_FB3_Pos (3U)
3767 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3768 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3769 #define CAN_F4R1_FB4_Pos (4U)
3770 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3771 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3772 #define CAN_F4R1_FB5_Pos (5U)
3773 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3774 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3775 #define CAN_F4R1_FB6_Pos (6U)
3776 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3777 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3778 #define CAN_F4R1_FB7_Pos (7U)
3779 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3780 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3781 #define CAN_F4R1_FB8_Pos (8U)
3782 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3783 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3784 #define CAN_F4R1_FB9_Pos (9U)
3785 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3786 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3787 #define CAN_F4R1_FB10_Pos (10U)
3788 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3789 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3790 #define CAN_F4R1_FB11_Pos (11U)
3791 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3792 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3793 #define CAN_F4R1_FB12_Pos (12U)
3794 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3795 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3796 #define CAN_F4R1_FB13_Pos (13U)
3797 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3798 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3799 #define CAN_F4R1_FB14_Pos (14U)
3800 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3801 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3802 #define CAN_F4R1_FB15_Pos (15U)
3803 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3804 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3805 #define CAN_F4R1_FB16_Pos (16U)
3806 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3807 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3808 #define CAN_F4R1_FB17_Pos (17U)
3809 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3810 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3811 #define CAN_F4R1_FB18_Pos (18U)
3812 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3813 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3814 #define CAN_F4R1_FB19_Pos (19U)
3815 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3816 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3817 #define CAN_F4R1_FB20_Pos (20U)
3818 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3819 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3820 #define CAN_F4R1_FB21_Pos (21U)
3821 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3822 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3823 #define CAN_F4R1_FB22_Pos (22U)
3824 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3825 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3826 #define CAN_F4R1_FB23_Pos (23U)
3827 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3828 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3829 #define CAN_F4R1_FB24_Pos (24U)
3830 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3831 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3832 #define CAN_F4R1_FB25_Pos (25U)
3833 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3834 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3835 #define CAN_F4R1_FB26_Pos (26U)
3836 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3837 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3838 #define CAN_F4R1_FB27_Pos (27U)
3839 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3840 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3841 #define CAN_F4R1_FB28_Pos (28U)
3842 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3843 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3844 #define CAN_F4R1_FB29_Pos (29U)
3845 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3846 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3847 #define CAN_F4R1_FB30_Pos (30U)
3848 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3849 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3850 #define CAN_F4R1_FB31_Pos (31U)
3851 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3852 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3854 /******************* Bit definition for CAN_F5R1 register *******************/
3855 #define CAN_F5R1_FB0_Pos (0U)
3856 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3857 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3858 #define CAN_F5R1_FB1_Pos (1U)
3859 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3860 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3861 #define CAN_F5R1_FB2_Pos (2U)
3862 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3863 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3864 #define CAN_F5R1_FB3_Pos (3U)
3865 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3866 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3867 #define CAN_F5R1_FB4_Pos (4U)
3868 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3869 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3870 #define CAN_F5R1_FB5_Pos (5U)
3871 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3872 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3873 #define CAN_F5R1_FB6_Pos (6U)
3874 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3875 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3876 #define CAN_F5R1_FB7_Pos (7U)
3877 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3878 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3879 #define CAN_F5R1_FB8_Pos (8U)
3880 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3881 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3882 #define CAN_F5R1_FB9_Pos (9U)
3883 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3884 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3885 #define CAN_F5R1_FB10_Pos (10U)
3886 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3887 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3888 #define CAN_F5R1_FB11_Pos (11U)
3889 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3890 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3891 #define CAN_F5R1_FB12_Pos (12U)
3892 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3893 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3894 #define CAN_F5R1_FB13_Pos (13U)
3895 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3896 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3897 #define CAN_F5R1_FB14_Pos (14U)
3898 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3899 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3900 #define CAN_F5R1_FB15_Pos (15U)
3901 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3902 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3903 #define CAN_F5R1_FB16_Pos (16U)
3904 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3905 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3906 #define CAN_F5R1_FB17_Pos (17U)
3907 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3908 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3909 #define CAN_F5R1_FB18_Pos (18U)
3910 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3911 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3912 #define CAN_F5R1_FB19_Pos (19U)
3913 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3914 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3915 #define CAN_F5R1_FB20_Pos (20U)
3916 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3917 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3918 #define CAN_F5R1_FB21_Pos (21U)
3919 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3920 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3921 #define CAN_F5R1_FB22_Pos (22U)
3922 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3923 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3924 #define CAN_F5R1_FB23_Pos (23U)
3925 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3926 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3927 #define CAN_F5R1_FB24_Pos (24U)
3928 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3929 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3930 #define CAN_F5R1_FB25_Pos (25U)
3931 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3932 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3933 #define CAN_F5R1_FB26_Pos (26U)
3934 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3935 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3936 #define CAN_F5R1_FB27_Pos (27U)
3937 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3938 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3939 #define CAN_F5R1_FB28_Pos (28U)
3940 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3941 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3942 #define CAN_F5R1_FB29_Pos (29U)
3943 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3944 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3945 #define CAN_F5R1_FB30_Pos (30U)
3946 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3947 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3948 #define CAN_F5R1_FB31_Pos (31U)
3949 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3950 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3952 /******************* Bit definition for CAN_F6R1 register *******************/
3953 #define CAN_F6R1_FB0_Pos (0U)
3954 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3955 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3956 #define CAN_F6R1_FB1_Pos (1U)
3957 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3958 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3959 #define CAN_F6R1_FB2_Pos (2U)
3960 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3961 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3962 #define CAN_F6R1_FB3_Pos (3U)
3963 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3964 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3965 #define CAN_F6R1_FB4_Pos (4U)
3966 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3967 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3968 #define CAN_F6R1_FB5_Pos (5U)
3969 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3970 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3971 #define CAN_F6R1_FB6_Pos (6U)
3972 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3973 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3974 #define CAN_F6R1_FB7_Pos (7U)
3975 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3976 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3977 #define CAN_F6R1_FB8_Pos (8U)
3978 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3979 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3980 #define CAN_F6R1_FB9_Pos (9U)
3981 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3982 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3983 #define CAN_F6R1_FB10_Pos (10U)
3984 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3985 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3986 #define CAN_F6R1_FB11_Pos (11U)
3987 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3988 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3989 #define CAN_F6R1_FB12_Pos (12U)
3990 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3991 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3992 #define CAN_F6R1_FB13_Pos (13U)
3993 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3994 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3995 #define CAN_F6R1_FB14_Pos (14U)
3996 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3997 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3998 #define CAN_F6R1_FB15_Pos (15U)
3999 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
4000 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
4001 #define CAN_F6R1_FB16_Pos (16U)
4002 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
4003 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
4004 #define CAN_F6R1_FB17_Pos (17U)
4005 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
4006 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
4007 #define CAN_F6R1_FB18_Pos (18U)
4008 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
4009 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
4010 #define CAN_F6R1_FB19_Pos (19U)
4011 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
4012 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
4013 #define CAN_F6R1_FB20_Pos (20U)
4014 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
4015 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
4016 #define CAN_F6R1_FB21_Pos (21U)
4017 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
4018 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
4019 #define CAN_F6R1_FB22_Pos (22U)
4020 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
4021 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
4022 #define CAN_F6R1_FB23_Pos (23U)
4023 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
4024 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
4025 #define CAN_F6R1_FB24_Pos (24U)
4026 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
4027 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
4028 #define CAN_F6R1_FB25_Pos (25U)
4029 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
4030 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
4031 #define CAN_F6R1_FB26_Pos (26U)
4032 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
4033 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
4034 #define CAN_F6R1_FB27_Pos (27U)
4035 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
4036 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
4037 #define CAN_F6R1_FB28_Pos (28U)
4038 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
4039 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
4040 #define CAN_F6R1_FB29_Pos (29U)
4041 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
4042 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
4043 #define CAN_F6R1_FB30_Pos (30U)
4044 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
4045 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
4046 #define CAN_F6R1_FB31_Pos (31U)
4047 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
4048 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
4050 /******************* Bit definition for CAN_F7R1 register *******************/
4051 #define CAN_F7R1_FB0_Pos (0U)
4052 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
4053 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
4054 #define CAN_F7R1_FB1_Pos (1U)
4055 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
4056 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
4057 #define CAN_F7R1_FB2_Pos (2U)
4058 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
4059 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
4060 #define CAN_F7R1_FB3_Pos (3U)
4061 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
4062 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
4063 #define CAN_F7R1_FB4_Pos (4U)
4064 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
4065 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
4066 #define CAN_F7R1_FB5_Pos (5U)
4067 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
4068 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
4069 #define CAN_F7R1_FB6_Pos (6U)
4070 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
4071 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
4072 #define CAN_F7R1_FB7_Pos (7U)
4073 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
4074 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
4075 #define CAN_F7R1_FB8_Pos (8U)
4076 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
4077 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
4078 #define CAN_F7R1_FB9_Pos (9U)
4079 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
4080 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
4081 #define CAN_F7R1_FB10_Pos (10U)
4082 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
4083 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
4084 #define CAN_F7R1_FB11_Pos (11U)
4085 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
4086 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
4087 #define CAN_F7R1_FB12_Pos (12U)
4088 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
4089 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
4090 #define CAN_F7R1_FB13_Pos (13U)
4091 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
4092 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
4093 #define CAN_F7R1_FB14_Pos (14U)
4094 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
4095 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
4096 #define CAN_F7R1_FB15_Pos (15U)
4097 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
4098 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
4099 #define CAN_F7R1_FB16_Pos (16U)
4100 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
4101 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
4102 #define CAN_F7R1_FB17_Pos (17U)
4103 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
4104 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
4105 #define CAN_F7R1_FB18_Pos (18U)
4106 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
4107 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
4108 #define CAN_F7R1_FB19_Pos (19U)
4109 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
4110 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
4111 #define CAN_F7R1_FB20_Pos (20U)
4112 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
4113 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
4114 #define CAN_F7R1_FB21_Pos (21U)
4115 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
4116 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
4117 #define CAN_F7R1_FB22_Pos (22U)
4118 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
4119 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
4120 #define CAN_F7R1_FB23_Pos (23U)
4121 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
4122 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
4123 #define CAN_F7R1_FB24_Pos (24U)
4124 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
4125 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
4126 #define CAN_F7R1_FB25_Pos (25U)
4127 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
4128 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
4129 #define CAN_F7R1_FB26_Pos (26U)
4130 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
4131 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
4132 #define CAN_F7R1_FB27_Pos (27U)
4133 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
4134 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
4135 #define CAN_F7R1_FB28_Pos (28U)
4136 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
4137 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
4138 #define CAN_F7R1_FB29_Pos (29U)
4139 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
4140 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
4141 #define CAN_F7R1_FB30_Pos (30U)
4142 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
4143 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
4144 #define CAN_F7R1_FB31_Pos (31U)
4145 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
4146 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
4148 /******************* Bit definition for CAN_F8R1 register *******************/
4149 #define CAN_F8R1_FB0_Pos (0U)
4150 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
4151 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
4152 #define CAN_F8R1_FB1_Pos (1U)
4153 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
4154 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
4155 #define CAN_F8R1_FB2_Pos (2U)
4156 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
4157 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
4158 #define CAN_F8R1_FB3_Pos (3U)
4159 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
4160 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
4161 #define CAN_F8R1_FB4_Pos (4U)
4162 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
4163 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
4164 #define CAN_F8R1_FB5_Pos (5U)
4165 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
4166 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
4167 #define CAN_F8R1_FB6_Pos (6U)
4168 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
4169 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
4170 #define CAN_F8R1_FB7_Pos (7U)
4171 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
4172 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
4173 #define CAN_F8R1_FB8_Pos (8U)
4174 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
4175 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
4176 #define CAN_F8R1_FB9_Pos (9U)
4177 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
4178 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
4179 #define CAN_F8R1_FB10_Pos (10U)
4180 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
4181 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
4182 #define CAN_F8R1_FB11_Pos (11U)
4183 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
4184 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
4185 #define CAN_F8R1_FB12_Pos (12U)
4186 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
4187 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
4188 #define CAN_F8R1_FB13_Pos (13U)
4189 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
4190 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
4191 #define CAN_F8R1_FB14_Pos (14U)
4192 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
4193 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
4194 #define CAN_F8R1_FB15_Pos (15U)
4195 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
4196 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
4197 #define CAN_F8R1_FB16_Pos (16U)
4198 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
4199 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
4200 #define CAN_F8R1_FB17_Pos (17U)
4201 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
4202 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
4203 #define CAN_F8R1_FB18_Pos (18U)
4204 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
4205 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
4206 #define CAN_F8R1_FB19_Pos (19U)
4207 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
4208 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
4209 #define CAN_F8R1_FB20_Pos (20U)
4210 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
4211 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
4212 #define CAN_F8R1_FB21_Pos (21U)
4213 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
4214 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
4215 #define CAN_F8R1_FB22_Pos (22U)
4216 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
4217 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
4218 #define CAN_F8R1_FB23_Pos (23U)
4219 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
4220 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
4221 #define CAN_F8R1_FB24_Pos (24U)
4222 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
4223 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
4224 #define CAN_F8R1_FB25_Pos (25U)
4225 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
4226 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
4227 #define CAN_F8R1_FB26_Pos (26U)
4228 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
4229 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
4230 #define CAN_F8R1_FB27_Pos (27U)
4231 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
4232 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
4233 #define CAN_F8R1_FB28_Pos (28U)
4234 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
4235 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
4236 #define CAN_F8R1_FB29_Pos (29U)
4237 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
4238 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
4239 #define CAN_F8R1_FB30_Pos (30U)
4240 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
4241 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
4242 #define CAN_F8R1_FB31_Pos (31U)
4243 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
4244 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
4246 /******************* Bit definition for CAN_F9R1 register *******************/
4247 #define CAN_F9R1_FB0_Pos (0U)
4248 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
4249 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
4250 #define CAN_F9R1_FB1_Pos (1U)
4251 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
4252 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
4253 #define CAN_F9R1_FB2_Pos (2U)
4254 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
4255 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
4256 #define CAN_F9R1_FB3_Pos (3U)
4257 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
4258 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
4259 #define CAN_F9R1_FB4_Pos (4U)
4260 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
4261 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
4262 #define CAN_F9R1_FB5_Pos (5U)
4263 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
4264 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
4265 #define CAN_F9R1_FB6_Pos (6U)
4266 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
4267 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
4268 #define CAN_F9R1_FB7_Pos (7U)
4269 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
4270 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
4271 #define CAN_F9R1_FB8_Pos (8U)
4272 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
4273 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
4274 #define CAN_F9R1_FB9_Pos (9U)
4275 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
4276 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
4277 #define CAN_F9R1_FB10_Pos (10U)
4278 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
4279 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
4280 #define CAN_F9R1_FB11_Pos (11U)
4281 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
4282 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
4283 #define CAN_F9R1_FB12_Pos (12U)
4284 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
4285 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
4286 #define CAN_F9R1_FB13_Pos (13U)
4287 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
4288 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
4289 #define CAN_F9R1_FB14_Pos (14U)
4290 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
4291 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
4292 #define CAN_F9R1_FB15_Pos (15U)
4293 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
4294 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
4295 #define CAN_F9R1_FB16_Pos (16U)
4296 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
4297 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
4298 #define CAN_F9R1_FB17_Pos (17U)
4299 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
4300 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
4301 #define CAN_F9R1_FB18_Pos (18U)
4302 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
4303 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
4304 #define CAN_F9R1_FB19_Pos (19U)
4305 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
4306 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
4307 #define CAN_F9R1_FB20_Pos (20U)
4308 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
4309 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
4310 #define CAN_F9R1_FB21_Pos (21U)
4311 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
4312 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
4313 #define CAN_F9R1_FB22_Pos (22U)
4314 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
4315 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
4316 #define CAN_F9R1_FB23_Pos (23U)
4317 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
4318 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
4319 #define CAN_F9R1_FB24_Pos (24U)
4320 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
4321 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
4322 #define CAN_F9R1_FB25_Pos (25U)
4323 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
4324 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
4325 #define CAN_F9R1_FB26_Pos (26U)
4326 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
4327 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
4328 #define CAN_F9R1_FB27_Pos (27U)
4329 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
4330 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
4331 #define CAN_F9R1_FB28_Pos (28U)
4332 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
4333 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
4334 #define CAN_F9R1_FB29_Pos (29U)
4335 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
4336 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
4337 #define CAN_F9R1_FB30_Pos (30U)
4338 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
4339 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
4340 #define CAN_F9R1_FB31_Pos (31U)
4341 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
4342 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
4344 /******************* Bit definition for CAN_F10R1 register ******************/
4345 #define CAN_F10R1_FB0_Pos (0U)
4346 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
4347 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
4348 #define CAN_F10R1_FB1_Pos (1U)
4349 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
4350 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
4351 #define CAN_F10R1_FB2_Pos (2U)
4352 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
4353 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
4354 #define CAN_F10R1_FB3_Pos (3U)
4355 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
4356 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
4357 #define CAN_F10R1_FB4_Pos (4U)
4358 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
4359 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
4360 #define CAN_F10R1_FB5_Pos (5U)
4361 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
4362 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
4363 #define CAN_F10R1_FB6_Pos (6U)
4364 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
4365 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
4366 #define CAN_F10R1_FB7_Pos (7U)
4367 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
4368 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
4369 #define CAN_F10R1_FB8_Pos (8U)
4370 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
4371 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
4372 #define CAN_F10R1_FB9_Pos (9U)
4373 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
4374 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
4375 #define CAN_F10R1_FB10_Pos (10U)
4376 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
4377 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
4378 #define CAN_F10R1_FB11_Pos (11U)
4379 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
4380 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
4381 #define CAN_F10R1_FB12_Pos (12U)
4382 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
4383 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
4384 #define CAN_F10R1_FB13_Pos (13U)
4385 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
4386 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
4387 #define CAN_F10R1_FB14_Pos (14U)
4388 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
4389 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
4390 #define CAN_F10R1_FB15_Pos (15U)
4391 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
4392 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
4393 #define CAN_F10R1_FB16_Pos (16U)
4394 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
4395 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
4396 #define CAN_F10R1_FB17_Pos (17U)
4397 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
4398 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
4399 #define CAN_F10R1_FB18_Pos (18U)
4400 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
4401 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
4402 #define CAN_F10R1_FB19_Pos (19U)
4403 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
4404 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
4405 #define CAN_F10R1_FB20_Pos (20U)
4406 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
4407 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
4408 #define CAN_F10R1_FB21_Pos (21U)
4409 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
4410 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
4411 #define CAN_F10R1_FB22_Pos (22U)
4412 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
4413 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
4414 #define CAN_F10R1_FB23_Pos (23U)
4415 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
4416 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
4417 #define CAN_F10R1_FB24_Pos (24U)
4418 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
4419 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
4420 #define CAN_F10R1_FB25_Pos (25U)
4421 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
4422 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
4423 #define CAN_F10R1_FB26_Pos (26U)
4424 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
4425 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
4426 #define CAN_F10R1_FB27_Pos (27U)
4427 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
4428 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
4429 #define CAN_F10R1_FB28_Pos (28U)
4430 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
4431 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
4432 #define CAN_F10R1_FB29_Pos (29U)
4433 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
4434 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
4435 #define CAN_F10R1_FB30_Pos (30U)
4436 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
4437 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
4438 #define CAN_F10R1_FB31_Pos (31U)
4439 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
4440 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
4442 /******************* Bit definition for CAN_F11R1 register ******************/
4443 #define CAN_F11R1_FB0_Pos (0U)
4444 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
4445 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
4446 #define CAN_F11R1_FB1_Pos (1U)
4447 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
4448 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
4449 #define CAN_F11R1_FB2_Pos (2U)
4450 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
4451 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
4452 #define CAN_F11R1_FB3_Pos (3U)
4453 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
4454 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
4455 #define CAN_F11R1_FB4_Pos (4U)
4456 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
4457 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
4458 #define CAN_F11R1_FB5_Pos (5U)
4459 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
4460 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4461 #define CAN_F11R1_FB6_Pos (6U)
4462 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4463 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4464 #define CAN_F11R1_FB7_Pos (7U)
4465 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4466 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4467 #define CAN_F11R1_FB8_Pos (8U)
4468 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4469 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4470 #define CAN_F11R1_FB9_Pos (9U)
4471 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4472 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4473 #define CAN_F11R1_FB10_Pos (10U)
4474 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4475 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4476 #define CAN_F11R1_FB11_Pos (11U)
4477 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4478 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4479 #define CAN_F11R1_FB12_Pos (12U)
4480 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4481 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4482 #define CAN_F11R1_FB13_Pos (13U)
4483 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4484 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4485 #define CAN_F11R1_FB14_Pos (14U)
4486 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4487 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4488 #define CAN_F11R1_FB15_Pos (15U)
4489 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4490 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4491 #define CAN_F11R1_FB16_Pos (16U)
4492 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4493 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4494 #define CAN_F11R1_FB17_Pos (17U)
4495 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4496 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4497 #define CAN_F11R1_FB18_Pos (18U)
4498 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4499 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4500 #define CAN_F11R1_FB19_Pos (19U)
4501 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4502 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4503 #define CAN_F11R1_FB20_Pos (20U)
4504 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4505 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4506 #define CAN_F11R1_FB21_Pos (21U)
4507 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4508 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4509 #define CAN_F11R1_FB22_Pos (22U)
4510 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4511 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4512 #define CAN_F11R1_FB23_Pos (23U)
4513 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4514 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4515 #define CAN_F11R1_FB24_Pos (24U)
4516 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4517 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4518 #define CAN_F11R1_FB25_Pos (25U)
4519 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4520 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4521 #define CAN_F11R1_FB26_Pos (26U)
4522 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4523 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4524 #define CAN_F11R1_FB27_Pos (27U)
4525 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4526 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4527 #define CAN_F11R1_FB28_Pos (28U)
4528 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4529 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4530 #define CAN_F11R1_FB29_Pos (29U)
4531 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4532 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4533 #define CAN_F11R1_FB30_Pos (30U)
4534 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4535 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4536 #define CAN_F11R1_FB31_Pos (31U)
4537 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4538 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4540 /******************* Bit definition for CAN_F12R1 register ******************/
4541 #define CAN_F12R1_FB0_Pos (0U)
4542 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4543 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4544 #define CAN_F12R1_FB1_Pos (1U)
4545 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4546 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4547 #define CAN_F12R1_FB2_Pos (2U)
4548 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4549 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4550 #define CAN_F12R1_FB3_Pos (3U)
4551 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4552 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4553 #define CAN_F12R1_FB4_Pos (4U)
4554 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4555 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4556 #define CAN_F12R1_FB5_Pos (5U)
4557 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4558 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4559 #define CAN_F12R1_FB6_Pos (6U)
4560 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4561 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4562 #define CAN_F12R1_FB7_Pos (7U)
4563 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4564 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4565 #define CAN_F12R1_FB8_Pos (8U)
4566 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4567 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4568 #define CAN_F12R1_FB9_Pos (9U)
4569 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4570 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4571 #define CAN_F12R1_FB10_Pos (10U)
4572 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4573 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4574 #define CAN_F12R1_FB11_Pos (11U)
4575 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4576 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4577 #define CAN_F12R1_FB12_Pos (12U)
4578 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4579 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4580 #define CAN_F12R1_FB13_Pos (13U)
4581 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4582 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4583 #define CAN_F12R1_FB14_Pos (14U)
4584 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4585 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4586 #define CAN_F12R1_FB15_Pos (15U)
4587 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4588 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4589 #define CAN_F12R1_FB16_Pos (16U)
4590 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4591 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4592 #define CAN_F12R1_FB17_Pos (17U)
4593 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4594 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4595 #define CAN_F12R1_FB18_Pos (18U)
4596 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4597 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4598 #define CAN_F12R1_FB19_Pos (19U)
4599 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4600 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4601 #define CAN_F12R1_FB20_Pos (20U)
4602 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4603 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4604 #define CAN_F12R1_FB21_Pos (21U)
4605 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4606 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4607 #define CAN_F12R1_FB22_Pos (22U)
4608 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4609 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4610 #define CAN_F12R1_FB23_Pos (23U)
4611 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4612 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4613 #define CAN_F12R1_FB24_Pos (24U)
4614 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4615 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4616 #define CAN_F12R1_FB25_Pos (25U)
4617 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4618 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4619 #define CAN_F12R1_FB26_Pos (26U)
4620 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4621 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4622 #define CAN_F12R1_FB27_Pos (27U)
4623 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4624 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4625 #define CAN_F12R1_FB28_Pos (28U)
4626 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4627 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4628 #define CAN_F12R1_FB29_Pos (29U)
4629 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4630 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4631 #define CAN_F12R1_FB30_Pos (30U)
4632 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4633 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4634 #define CAN_F12R1_FB31_Pos (31U)
4635 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4636 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4638 /******************* Bit definition for CAN_F13R1 register ******************/
4639 #define CAN_F13R1_FB0_Pos (0U)
4640 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4641 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4642 #define CAN_F13R1_FB1_Pos (1U)
4643 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4644 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4645 #define CAN_F13R1_FB2_Pos (2U)
4646 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4647 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4648 #define CAN_F13R1_FB3_Pos (3U)
4649 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4650 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4651 #define CAN_F13R1_FB4_Pos (4U)
4652 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4653 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4654 #define CAN_F13R1_FB5_Pos (5U)
4655 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4656 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4657 #define CAN_F13R1_FB6_Pos (6U)
4658 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4659 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4660 #define CAN_F13R1_FB7_Pos (7U)
4661 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4662 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4663 #define CAN_F13R1_FB8_Pos (8U)
4664 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4665 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4666 #define CAN_F13R1_FB9_Pos (9U)
4667 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4668 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4669 #define CAN_F13R1_FB10_Pos (10U)
4670 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4671 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4672 #define CAN_F13R1_FB11_Pos (11U)
4673 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4674 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4675 #define CAN_F13R1_FB12_Pos (12U)
4676 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4677 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4678 #define CAN_F13R1_FB13_Pos (13U)
4679 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4680 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4681 #define CAN_F13R1_FB14_Pos (14U)
4682 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4683 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4684 #define CAN_F13R1_FB15_Pos (15U)
4685 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4686 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4687 #define CAN_F13R1_FB16_Pos (16U)
4688 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4689 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4690 #define CAN_F13R1_FB17_Pos (17U)
4691 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4692 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4693 #define CAN_F13R1_FB18_Pos (18U)
4694 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4695 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4696 #define CAN_F13R1_FB19_Pos (19U)
4697 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4698 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4699 #define CAN_F13R1_FB20_Pos (20U)
4700 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4701 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4702 #define CAN_F13R1_FB21_Pos (21U)
4703 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4704 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4705 #define CAN_F13R1_FB22_Pos (22U)
4706 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4707 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4708 #define CAN_F13R1_FB23_Pos (23U)
4709 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4710 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4711 #define CAN_F13R1_FB24_Pos (24U)
4712 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4713 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4714 #define CAN_F13R1_FB25_Pos (25U)
4715 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4716 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4717 #define CAN_F13R1_FB26_Pos (26U)
4718 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4719 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4720 #define CAN_F13R1_FB27_Pos (27U)
4721 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4722 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4723 #define CAN_F13R1_FB28_Pos (28U)
4724 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4725 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4726 #define CAN_F13R1_FB29_Pos (29U)
4727 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4728 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4729 #define CAN_F13R1_FB30_Pos (30U)
4730 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4731 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4732 #define CAN_F13R1_FB31_Pos (31U)
4733 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4734 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4736 /******************* Bit definition for CAN_F0R2 register *******************/
4737 #define CAN_F0R2_FB0_Pos (0U)
4738 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4739 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4740 #define CAN_F0R2_FB1_Pos (1U)
4741 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4742 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4743 #define CAN_F0R2_FB2_Pos (2U)
4744 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4745 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4746 #define CAN_F0R2_FB3_Pos (3U)
4747 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4748 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4749 #define CAN_F0R2_FB4_Pos (4U)
4750 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4751 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4752 #define CAN_F0R2_FB5_Pos (5U)
4753 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4754 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4755 #define CAN_F0R2_FB6_Pos (6U)
4756 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4757 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4758 #define CAN_F0R2_FB7_Pos (7U)
4759 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4760 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4761 #define CAN_F0R2_FB8_Pos (8U)
4762 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4763 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4764 #define CAN_F0R2_FB9_Pos (9U)
4765 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4766 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4767 #define CAN_F0R2_FB10_Pos (10U)
4768 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4769 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4770 #define CAN_F0R2_FB11_Pos (11U)
4771 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4772 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4773 #define CAN_F0R2_FB12_Pos (12U)
4774 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4775 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4776 #define CAN_F0R2_FB13_Pos (13U)
4777 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4778 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4779 #define CAN_F0R2_FB14_Pos (14U)
4780 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4781 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4782 #define CAN_F0R2_FB15_Pos (15U)
4783 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4784 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4785 #define CAN_F0R2_FB16_Pos (16U)
4786 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4787 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4788 #define CAN_F0R2_FB17_Pos (17U)
4789 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4790 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4791 #define CAN_F0R2_FB18_Pos (18U)
4792 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4793 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4794 #define CAN_F0R2_FB19_Pos (19U)
4795 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4796 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4797 #define CAN_F0R2_FB20_Pos (20U)
4798 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4799 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4800 #define CAN_F0R2_FB21_Pos (21U)
4801 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4802 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4803 #define CAN_F0R2_FB22_Pos (22U)
4804 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4805 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4806 #define CAN_F0R2_FB23_Pos (23U)
4807 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4808 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4809 #define CAN_F0R2_FB24_Pos (24U)
4810 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4811 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4812 #define CAN_F0R2_FB25_Pos (25U)
4813 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4814 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4815 #define CAN_F0R2_FB26_Pos (26U)
4816 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4817 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4818 #define CAN_F0R2_FB27_Pos (27U)
4819 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4820 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4821 #define CAN_F0R2_FB28_Pos (28U)
4822 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4823 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4824 #define CAN_F0R2_FB29_Pos (29U)
4825 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4826 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4827 #define CAN_F0R2_FB30_Pos (30U)
4828 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4829 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4830 #define CAN_F0R2_FB31_Pos (31U)
4831 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4832 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4834 /******************* Bit definition for CAN_F1R2 register *******************/
4835 #define CAN_F1R2_FB0_Pos (0U)
4836 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4837 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4838 #define CAN_F1R2_FB1_Pos (1U)
4839 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4840 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4841 #define CAN_F1R2_FB2_Pos (2U)
4842 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4843 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4844 #define CAN_F1R2_FB3_Pos (3U)
4845 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4846 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4847 #define CAN_F1R2_FB4_Pos (4U)
4848 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4849 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4850 #define CAN_F1R2_FB5_Pos (5U)
4851 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4852 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4853 #define CAN_F1R2_FB6_Pos (6U)
4854 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4855 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4856 #define CAN_F1R2_FB7_Pos (7U)
4857 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4858 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4859 #define CAN_F1R2_FB8_Pos (8U)
4860 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4861 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4862 #define CAN_F1R2_FB9_Pos (9U)
4863 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4864 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4865 #define CAN_F1R2_FB10_Pos (10U)
4866 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4867 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4868 #define CAN_F1R2_FB11_Pos (11U)
4869 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4870 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4871 #define CAN_F1R2_FB12_Pos (12U)
4872 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4873 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4874 #define CAN_F1R2_FB13_Pos (13U)
4875 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4876 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4877 #define CAN_F1R2_FB14_Pos (14U)
4878 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4879 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4880 #define CAN_F1R2_FB15_Pos (15U)
4881 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4882 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4883 #define CAN_F1R2_FB16_Pos (16U)
4884 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4885 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4886 #define CAN_F1R2_FB17_Pos (17U)
4887 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4888 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4889 #define CAN_F1R2_FB18_Pos (18U)
4890 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4891 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4892 #define CAN_F1R2_FB19_Pos (19U)
4893 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4894 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4895 #define CAN_F1R2_FB20_Pos (20U)
4896 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4897 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4898 #define CAN_F1R2_FB21_Pos (21U)
4899 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4900 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4901 #define CAN_F1R2_FB22_Pos (22U)
4902 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4903 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4904 #define CAN_F1R2_FB23_Pos (23U)
4905 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4906 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4907 #define CAN_F1R2_FB24_Pos (24U)
4908 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4909 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4910 #define CAN_F1R2_FB25_Pos (25U)
4911 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4912 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4913 #define CAN_F1R2_FB26_Pos (26U)
4914 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4915 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4916 #define CAN_F1R2_FB27_Pos (27U)
4917 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4918 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4919 #define CAN_F1R2_FB28_Pos (28U)
4920 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4921 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4922 #define CAN_F1R2_FB29_Pos (29U)
4923 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4924 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4925 #define CAN_F1R2_FB30_Pos (30U)
4926 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4927 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4928 #define CAN_F1R2_FB31_Pos (31U)
4929 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4930 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4932 /******************* Bit definition for CAN_F2R2 register *******************/
4933 #define CAN_F2R2_FB0_Pos (0U)
4934 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4935 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4936 #define CAN_F2R2_FB1_Pos (1U)
4937 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4938 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4939 #define CAN_F2R2_FB2_Pos (2U)
4940 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4941 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4942 #define CAN_F2R2_FB3_Pos (3U)
4943 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4944 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4945 #define CAN_F2R2_FB4_Pos (4U)
4946 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4947 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4948 #define CAN_F2R2_FB5_Pos (5U)
4949 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4950 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4951 #define CAN_F2R2_FB6_Pos (6U)
4952 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4953 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4954 #define CAN_F2R2_FB7_Pos (7U)
4955 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4956 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4957 #define CAN_F2R2_FB8_Pos (8U)
4958 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4959 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4960 #define CAN_F2R2_FB9_Pos (9U)
4961 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4962 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4963 #define CAN_F2R2_FB10_Pos (10U)
4964 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4965 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4966 #define CAN_F2R2_FB11_Pos (11U)
4967 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4968 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4969 #define CAN_F2R2_FB12_Pos (12U)
4970 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4971 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4972 #define CAN_F2R2_FB13_Pos (13U)
4973 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4974 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4975 #define CAN_F2R2_FB14_Pos (14U)
4976 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4977 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4978 #define CAN_F2R2_FB15_Pos (15U)
4979 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4980 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4981 #define CAN_F2R2_FB16_Pos (16U)
4982 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4983 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4984 #define CAN_F2R2_FB17_Pos (17U)
4985 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4986 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4987 #define CAN_F2R2_FB18_Pos (18U)
4988 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4989 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4990 #define CAN_F2R2_FB19_Pos (19U)
4991 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4992 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4993 #define CAN_F2R2_FB20_Pos (20U)
4994 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4995 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4996 #define CAN_F2R2_FB21_Pos (21U)
4997 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4998 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4999 #define CAN_F2R2_FB22_Pos (22U)
5000 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
5001 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
5002 #define CAN_F2R2_FB23_Pos (23U)
5003 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
5004 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
5005 #define CAN_F2R2_FB24_Pos (24U)
5006 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
5007 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
5008 #define CAN_F2R2_FB25_Pos (25U)
5009 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
5010 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
5011 #define CAN_F2R2_FB26_Pos (26U)
5012 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
5013 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
5014 #define CAN_F2R2_FB27_Pos (27U)
5015 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
5016 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
5017 #define CAN_F2R2_FB28_Pos (28U)
5018 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
5019 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
5020 #define CAN_F2R2_FB29_Pos (29U)
5021 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
5022 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
5023 #define CAN_F2R2_FB30_Pos (30U)
5024 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
5025 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
5026 #define CAN_F2R2_FB31_Pos (31U)
5027 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
5028 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
5030 /******************* Bit definition for CAN_F3R2 register *******************/
5031 #define CAN_F3R2_FB0_Pos (0U)
5032 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
5033 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
5034 #define CAN_F3R2_FB1_Pos (1U)
5035 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
5036 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
5037 #define CAN_F3R2_FB2_Pos (2U)
5038 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
5039 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
5040 #define CAN_F3R2_FB3_Pos (3U)
5041 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
5042 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
5043 #define CAN_F3R2_FB4_Pos (4U)
5044 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
5045 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
5046 #define CAN_F3R2_FB5_Pos (5U)
5047 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
5048 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
5049 #define CAN_F3R2_FB6_Pos (6U)
5050 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
5051 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
5052 #define CAN_F3R2_FB7_Pos (7U)
5053 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
5054 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
5055 #define CAN_F3R2_FB8_Pos (8U)
5056 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
5057 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
5058 #define CAN_F3R2_FB9_Pos (9U)
5059 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
5060 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
5061 #define CAN_F3R2_FB10_Pos (10U)
5062 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
5063 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
5064 #define CAN_F3R2_FB11_Pos (11U)
5065 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
5066 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
5067 #define CAN_F3R2_FB12_Pos (12U)
5068 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
5069 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
5070 #define CAN_F3R2_FB13_Pos (13U)
5071 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
5072 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
5073 #define CAN_F3R2_FB14_Pos (14U)
5074 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
5075 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
5076 #define CAN_F3R2_FB15_Pos (15U)
5077 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
5078 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
5079 #define CAN_F3R2_FB16_Pos (16U)
5080 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
5081 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
5082 #define CAN_F3R2_FB17_Pos (17U)
5083 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
5084 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
5085 #define CAN_F3R2_FB18_Pos (18U)
5086 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
5087 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
5088 #define CAN_F3R2_FB19_Pos (19U)
5089 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
5090 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
5091 #define CAN_F3R2_FB20_Pos (20U)
5092 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
5093 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
5094 #define CAN_F3R2_FB21_Pos (21U)
5095 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
5096 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
5097 #define CAN_F3R2_FB22_Pos (22U)
5098 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
5099 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
5100 #define CAN_F3R2_FB23_Pos (23U)
5101 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
5102 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
5103 #define CAN_F3R2_FB24_Pos (24U)
5104 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
5105 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
5106 #define CAN_F3R2_FB25_Pos (25U)
5107 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
5108 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
5109 #define CAN_F3R2_FB26_Pos (26U)
5110 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
5111 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
5112 #define CAN_F3R2_FB27_Pos (27U)
5113 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
5114 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
5115 #define CAN_F3R2_FB28_Pos (28U)
5116 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
5117 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
5118 #define CAN_F3R2_FB29_Pos (29U)
5119 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
5120 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
5121 #define CAN_F3R2_FB30_Pos (30U)
5122 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
5123 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
5124 #define CAN_F3R2_FB31_Pos (31U)
5125 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
5126 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
5128 /******************* Bit definition for CAN_F4R2 register *******************/
5129 #define CAN_F4R2_FB0_Pos (0U)
5130 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
5131 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
5132 #define CAN_F4R2_FB1_Pos (1U)
5133 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
5134 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
5135 #define CAN_F4R2_FB2_Pos (2U)
5136 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
5137 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
5138 #define CAN_F4R2_FB3_Pos (3U)
5139 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
5140 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
5141 #define CAN_F4R2_FB4_Pos (4U)
5142 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
5143 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
5144 #define CAN_F4R2_FB5_Pos (5U)
5145 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
5146 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
5147 #define CAN_F4R2_FB6_Pos (6U)
5148 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
5149 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
5150 #define CAN_F4R2_FB7_Pos (7U)
5151 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
5152 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
5153 #define CAN_F4R2_FB8_Pos (8U)
5154 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
5155 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
5156 #define CAN_F4R2_FB9_Pos (9U)
5157 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
5158 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
5159 #define CAN_F4R2_FB10_Pos (10U)
5160 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
5161 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
5162 #define CAN_F4R2_FB11_Pos (11U)
5163 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
5164 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
5165 #define CAN_F4R2_FB12_Pos (12U)
5166 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
5167 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
5168 #define CAN_F4R2_FB13_Pos (13U)
5169 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
5170 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
5171 #define CAN_F4R2_FB14_Pos (14U)
5172 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
5173 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
5174 #define CAN_F4R2_FB15_Pos (15U)
5175 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
5176 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
5177 #define CAN_F4R2_FB16_Pos (16U)
5178 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
5179 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
5180 #define CAN_F4R2_FB17_Pos (17U)
5181 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
5182 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
5183 #define CAN_F4R2_FB18_Pos (18U)
5184 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
5185 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
5186 #define CAN_F4R2_FB19_Pos (19U)
5187 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
5188 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
5189 #define CAN_F4R2_FB20_Pos (20U)
5190 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
5191 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
5192 #define CAN_F4R2_FB21_Pos (21U)
5193 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
5194 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
5195 #define CAN_F4R2_FB22_Pos (22U)
5196 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
5197 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
5198 #define CAN_F4R2_FB23_Pos (23U)
5199 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
5200 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
5201 #define CAN_F4R2_FB24_Pos (24U)
5202 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
5203 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
5204 #define CAN_F4R2_FB25_Pos (25U)
5205 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
5206 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
5207 #define CAN_F4R2_FB26_Pos (26U)
5208 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
5209 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
5210 #define CAN_F4R2_FB27_Pos (27U)
5211 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
5212 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
5213 #define CAN_F4R2_FB28_Pos (28U)
5214 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
5215 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
5216 #define CAN_F4R2_FB29_Pos (29U)
5217 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
5218 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
5219 #define CAN_F4R2_FB30_Pos (30U)
5220 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
5221 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
5222 #define CAN_F4R2_FB31_Pos (31U)
5223 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
5224 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
5226 /******************* Bit definition for CAN_F5R2 register *******************/
5227 #define CAN_F5R2_FB0_Pos (0U)
5228 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
5229 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
5230 #define CAN_F5R2_FB1_Pos (1U)
5231 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
5232 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
5233 #define CAN_F5R2_FB2_Pos (2U)
5234 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
5235 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
5236 #define CAN_F5R2_FB3_Pos (3U)
5237 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
5238 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
5239 #define CAN_F5R2_FB4_Pos (4U)
5240 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
5241 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
5242 #define CAN_F5R2_FB5_Pos (5U)
5243 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
5244 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
5245 #define CAN_F5R2_FB6_Pos (6U)
5246 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
5247 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
5248 #define CAN_F5R2_FB7_Pos (7U)
5249 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
5250 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
5251 #define CAN_F5R2_FB8_Pos (8U)
5252 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
5253 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
5254 #define CAN_F5R2_FB9_Pos (9U)
5255 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
5256 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
5257 #define CAN_F5R2_FB10_Pos (10U)
5258 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
5259 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
5260 #define CAN_F5R2_FB11_Pos (11U)
5261 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
5262 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
5263 #define CAN_F5R2_FB12_Pos (12U)
5264 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
5265 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
5266 #define CAN_F5R2_FB13_Pos (13U)
5267 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
5268 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
5269 #define CAN_F5R2_FB14_Pos (14U)
5270 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
5271 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
5272 #define CAN_F5R2_FB15_Pos (15U)
5273 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
5274 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
5275 #define CAN_F5R2_FB16_Pos (16U)
5276 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
5277 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
5278 #define CAN_F5R2_FB17_Pos (17U)
5279 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
5280 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
5281 #define CAN_F5R2_FB18_Pos (18U)
5282 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
5283 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
5284 #define CAN_F5R2_FB19_Pos (19U)
5285 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
5286 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
5287 #define CAN_F5R2_FB20_Pos (20U)
5288 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
5289 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
5290 #define CAN_F5R2_FB21_Pos (21U)
5291 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
5292 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
5293 #define CAN_F5R2_FB22_Pos (22U)
5294 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
5295 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
5296 #define CAN_F5R2_FB23_Pos (23U)
5297 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
5298 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
5299 #define CAN_F5R2_FB24_Pos (24U)
5300 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
5301 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
5302 #define CAN_F5R2_FB25_Pos (25U)
5303 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
5304 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
5305 #define CAN_F5R2_FB26_Pos (26U)
5306 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
5307 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
5308 #define CAN_F5R2_FB27_Pos (27U)
5309 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
5310 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
5311 #define CAN_F5R2_FB28_Pos (28U)
5312 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
5313 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
5314 #define CAN_F5R2_FB29_Pos (29U)
5315 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
5316 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
5317 #define CAN_F5R2_FB30_Pos (30U)
5318 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
5319 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
5320 #define CAN_F5R2_FB31_Pos (31U)
5321 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
5322 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
5324 /******************* Bit definition for CAN_F6R2 register *******************/
5325 #define CAN_F6R2_FB0_Pos (0U)
5326 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
5327 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
5328 #define CAN_F6R2_FB1_Pos (1U)
5329 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
5330 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
5331 #define CAN_F6R2_FB2_Pos (2U)
5332 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
5333 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
5334 #define CAN_F6R2_FB3_Pos (3U)
5335 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
5336 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
5337 #define CAN_F6R2_FB4_Pos (4U)
5338 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
5339 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
5340 #define CAN_F6R2_FB5_Pos (5U)
5341 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
5342 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
5343 #define CAN_F6R2_FB6_Pos (6U)
5344 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
5345 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
5346 #define CAN_F6R2_FB7_Pos (7U)
5347 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
5348 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
5349 #define CAN_F6R2_FB8_Pos (8U)
5350 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
5351 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
5352 #define CAN_F6R2_FB9_Pos (9U)
5353 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
5354 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
5355 #define CAN_F6R2_FB10_Pos (10U)
5356 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
5357 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
5358 #define CAN_F6R2_FB11_Pos (11U)
5359 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
5360 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
5361 #define CAN_F6R2_FB12_Pos (12U)
5362 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
5363 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
5364 #define CAN_F6R2_FB13_Pos (13U)
5365 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
5366 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
5367 #define CAN_F6R2_FB14_Pos (14U)
5368 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
5369 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
5370 #define CAN_F6R2_FB15_Pos (15U)
5371 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
5372 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
5373 #define CAN_F6R2_FB16_Pos (16U)
5374 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
5375 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
5376 #define CAN_F6R2_FB17_Pos (17U)
5377 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
5378 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
5379 #define CAN_F6R2_FB18_Pos (18U)
5380 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
5381 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
5382 #define CAN_F6R2_FB19_Pos (19U)
5383 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
5384 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
5385 #define CAN_F6R2_FB20_Pos (20U)
5386 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
5387 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
5388 #define CAN_F6R2_FB21_Pos (21U)
5389 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
5390 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
5391 #define CAN_F6R2_FB22_Pos (22U)
5392 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
5393 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
5394 #define CAN_F6R2_FB23_Pos (23U)
5395 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
5396 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
5397 #define CAN_F6R2_FB24_Pos (24U)
5398 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
5399 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
5400 #define CAN_F6R2_FB25_Pos (25U)
5401 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
5402 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
5403 #define CAN_F6R2_FB26_Pos (26U)
5404 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
5405 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
5406 #define CAN_F6R2_FB27_Pos (27U)
5407 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
5408 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
5409 #define CAN_F6R2_FB28_Pos (28U)
5410 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
5411 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
5412 #define CAN_F6R2_FB29_Pos (29U)
5413 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
5414 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
5415 #define CAN_F6R2_FB30_Pos (30U)
5416 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
5417 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
5418 #define CAN_F6R2_FB31_Pos (31U)
5419 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
5420 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
5422 /******************* Bit definition for CAN_F7R2 register *******************/
5423 #define CAN_F7R2_FB0_Pos (0U)
5424 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
5425 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
5426 #define CAN_F7R2_FB1_Pos (1U)
5427 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
5428 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
5429 #define CAN_F7R2_FB2_Pos (2U)
5430 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
5431 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
5432 #define CAN_F7R2_FB3_Pos (3U)
5433 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
5434 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
5435 #define CAN_F7R2_FB4_Pos (4U)
5436 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
5437 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
5438 #define CAN_F7R2_FB5_Pos (5U)
5439 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
5440 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
5441 #define CAN_F7R2_FB6_Pos (6U)
5442 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
5443 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
5444 #define CAN_F7R2_FB7_Pos (7U)
5445 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
5446 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
5447 #define CAN_F7R2_FB8_Pos (8U)
5448 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
5449 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
5450 #define CAN_F7R2_FB9_Pos (9U)
5451 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
5452 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
5453 #define CAN_F7R2_FB10_Pos (10U)
5454 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
5455 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
5456 #define CAN_F7R2_FB11_Pos (11U)
5457 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
5458 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
5459 #define CAN_F7R2_FB12_Pos (12U)
5460 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5461 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5462 #define CAN_F7R2_FB13_Pos (13U)
5463 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5464 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5465 #define CAN_F7R2_FB14_Pos (14U)
5466 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5467 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5468 #define CAN_F7R2_FB15_Pos (15U)
5469 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5470 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5471 #define CAN_F7R2_FB16_Pos (16U)
5472 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5473 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5474 #define CAN_F7R2_FB17_Pos (17U)
5475 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5476 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5477 #define CAN_F7R2_FB18_Pos (18U)
5478 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5479 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5480 #define CAN_F7R2_FB19_Pos (19U)
5481 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5482 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5483 #define CAN_F7R2_FB20_Pos (20U)
5484 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5485 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5486 #define CAN_F7R2_FB21_Pos (21U)
5487 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5488 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5489 #define CAN_F7R2_FB22_Pos (22U)
5490 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5491 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5492 #define CAN_F7R2_FB23_Pos (23U)
5493 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5494 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5495 #define CAN_F7R2_FB24_Pos (24U)
5496 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5497 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5498 #define CAN_F7R2_FB25_Pos (25U)
5499 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5500 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5501 #define CAN_F7R2_FB26_Pos (26U)
5502 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5503 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5504 #define CAN_F7R2_FB27_Pos (27U)
5505 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5506 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5507 #define CAN_F7R2_FB28_Pos (28U)
5508 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5509 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5510 #define CAN_F7R2_FB29_Pos (29U)
5511 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5512 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5513 #define CAN_F7R2_FB30_Pos (30U)
5514 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5515 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5516 #define CAN_F7R2_FB31_Pos (31U)
5517 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5518 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5520 /******************* Bit definition for CAN_F8R2 register *******************/
5521 #define CAN_F8R2_FB0_Pos (0U)
5522 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5523 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5524 #define CAN_F8R2_FB1_Pos (1U)
5525 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5526 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5527 #define CAN_F8R2_FB2_Pos (2U)
5528 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5529 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5530 #define CAN_F8R2_FB3_Pos (3U)
5531 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5532 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5533 #define CAN_F8R2_FB4_Pos (4U)
5534 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5535 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5536 #define CAN_F8R2_FB5_Pos (5U)
5537 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5538 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5539 #define CAN_F8R2_FB6_Pos (6U)
5540 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5541 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5542 #define CAN_F8R2_FB7_Pos (7U)
5543 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5544 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5545 #define CAN_F8R2_FB8_Pos (8U)
5546 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5547 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5548 #define CAN_F8R2_FB9_Pos (9U)
5549 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5550 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5551 #define CAN_F8R2_FB10_Pos (10U)
5552 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5553 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5554 #define CAN_F8R2_FB11_Pos (11U)
5555 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5556 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5557 #define CAN_F8R2_FB12_Pos (12U)
5558 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5559 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5560 #define CAN_F8R2_FB13_Pos (13U)
5561 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5562 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5563 #define CAN_F8R2_FB14_Pos (14U)
5564 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5565 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5566 #define CAN_F8R2_FB15_Pos (15U)
5567 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5568 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5569 #define CAN_F8R2_FB16_Pos (16U)
5570 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5571 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5572 #define CAN_F8R2_FB17_Pos (17U)
5573 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5574 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5575 #define CAN_F8R2_FB18_Pos (18U)
5576 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5577 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5578 #define CAN_F8R2_FB19_Pos (19U)
5579 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5580 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5581 #define CAN_F8R2_FB20_Pos (20U)
5582 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5583 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5584 #define CAN_F8R2_FB21_Pos (21U)
5585 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5586 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5587 #define CAN_F8R2_FB22_Pos (22U)
5588 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5589 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5590 #define CAN_F8R2_FB23_Pos (23U)
5591 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5592 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5593 #define CAN_F8R2_FB24_Pos (24U)
5594 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5595 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5596 #define CAN_F8R2_FB25_Pos (25U)
5597 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5598 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5599 #define CAN_F8R2_FB26_Pos (26U)
5600 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5601 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5602 #define CAN_F8R2_FB27_Pos (27U)
5603 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5604 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5605 #define CAN_F8R2_FB28_Pos (28U)
5606 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5607 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5608 #define CAN_F8R2_FB29_Pos (29U)
5609 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5610 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5611 #define CAN_F8R2_FB30_Pos (30U)
5612 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5613 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5614 #define CAN_F8R2_FB31_Pos (31U)
5615 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5616 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5618 /******************* Bit definition for CAN_F9R2 register *******************/
5619 #define CAN_F9R2_FB0_Pos (0U)
5620 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5621 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5622 #define CAN_F9R2_FB1_Pos (1U)
5623 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5624 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5625 #define CAN_F9R2_FB2_Pos (2U)
5626 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5627 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5628 #define CAN_F9R2_FB3_Pos (3U)
5629 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5630 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5631 #define CAN_F9R2_FB4_Pos (4U)
5632 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5633 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5634 #define CAN_F9R2_FB5_Pos (5U)
5635 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5636 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5637 #define CAN_F9R2_FB6_Pos (6U)
5638 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5639 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5640 #define CAN_F9R2_FB7_Pos (7U)
5641 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5642 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5643 #define CAN_F9R2_FB8_Pos (8U)
5644 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5645 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5646 #define CAN_F9R2_FB9_Pos (9U)
5647 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5648 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5649 #define CAN_F9R2_FB10_Pos (10U)
5650 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5651 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5652 #define CAN_F9R2_FB11_Pos (11U)
5653 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5654 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5655 #define CAN_F9R2_FB12_Pos (12U)
5656 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5657 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5658 #define CAN_F9R2_FB13_Pos (13U)
5659 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5660 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5661 #define CAN_F9R2_FB14_Pos (14U)
5662 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5663 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5664 #define CAN_F9R2_FB15_Pos (15U)
5665 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5666 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5667 #define CAN_F9R2_FB16_Pos (16U)
5668 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5669 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5670 #define CAN_F9R2_FB17_Pos (17U)
5671 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5672 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5673 #define CAN_F9R2_FB18_Pos (18U)
5674 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5675 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5676 #define CAN_F9R2_FB19_Pos (19U)
5677 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5678 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5679 #define CAN_F9R2_FB20_Pos (20U)
5680 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5681 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5682 #define CAN_F9R2_FB21_Pos (21U)
5683 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5684 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5685 #define CAN_F9R2_FB22_Pos (22U)
5686 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5687 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5688 #define CAN_F9R2_FB23_Pos (23U)
5689 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5690 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5691 #define CAN_F9R2_FB24_Pos (24U)
5692 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5693 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5694 #define CAN_F9R2_FB25_Pos (25U)
5695 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5696 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5697 #define CAN_F9R2_FB26_Pos (26U)
5698 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5699 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5700 #define CAN_F9R2_FB27_Pos (27U)
5701 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5702 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5703 #define CAN_F9R2_FB28_Pos (28U)
5704 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5705 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5706 #define CAN_F9R2_FB29_Pos (29U)
5707 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5708 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5709 #define CAN_F9R2_FB30_Pos (30U)
5710 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5711 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5712 #define CAN_F9R2_FB31_Pos (31U)
5713 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5714 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5716 /******************* Bit definition for CAN_F10R2 register ******************/
5717 #define CAN_F10R2_FB0_Pos (0U)
5718 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5719 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5720 #define CAN_F10R2_FB1_Pos (1U)
5721 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5722 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5723 #define CAN_F10R2_FB2_Pos (2U)
5724 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5725 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5726 #define CAN_F10R2_FB3_Pos (3U)
5727 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5728 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5729 #define CAN_F10R2_FB4_Pos (4U)
5730 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5731 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5732 #define CAN_F10R2_FB5_Pos (5U)
5733 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5734 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5735 #define CAN_F10R2_FB6_Pos (6U)
5736 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5737 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5738 #define CAN_F10R2_FB7_Pos (7U)
5739 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5740 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5741 #define CAN_F10R2_FB8_Pos (8U)
5742 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5743 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5744 #define CAN_F10R2_FB9_Pos (9U)
5745 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5746 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5747 #define CAN_F10R2_FB10_Pos (10U)
5748 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5749 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5750 #define CAN_F10R2_FB11_Pos (11U)
5751 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5752 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5753 #define CAN_F10R2_FB12_Pos (12U)
5754 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5755 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5756 #define CAN_F10R2_FB13_Pos (13U)
5757 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5758 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5759 #define CAN_F10R2_FB14_Pos (14U)
5760 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5761 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5762 #define CAN_F10R2_FB15_Pos (15U)
5763 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5764 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5765 #define CAN_F10R2_FB16_Pos (16U)
5766 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5767 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5768 #define CAN_F10R2_FB17_Pos (17U)
5769 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5770 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5771 #define CAN_F10R2_FB18_Pos (18U)
5772 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5773 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5774 #define CAN_F10R2_FB19_Pos (19U)
5775 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5776 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5777 #define CAN_F10R2_FB20_Pos (20U)
5778 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5779 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5780 #define CAN_F10R2_FB21_Pos (21U)
5781 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5782 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5783 #define CAN_F10R2_FB22_Pos (22U)
5784 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5785 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5786 #define CAN_F10R2_FB23_Pos (23U)
5787 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5788 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5789 #define CAN_F10R2_FB24_Pos (24U)
5790 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5791 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5792 #define CAN_F10R2_FB25_Pos (25U)
5793 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5794 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5795 #define CAN_F10R2_FB26_Pos (26U)
5796 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5797 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5798 #define CAN_F10R2_FB27_Pos (27U)
5799 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5800 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5801 #define CAN_F10R2_FB28_Pos (28U)
5802 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5803 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5804 #define CAN_F10R2_FB29_Pos (29U)
5805 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5806 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5807 #define CAN_F10R2_FB30_Pos (30U)
5808 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5809 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5810 #define CAN_F10R2_FB31_Pos (31U)
5811 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5812 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5814 /******************* Bit definition for CAN_F11R2 register ******************/
5815 #define CAN_F11R2_FB0_Pos (0U)
5816 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5817 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5818 #define CAN_F11R2_FB1_Pos (1U)
5819 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5820 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5821 #define CAN_F11R2_FB2_Pos (2U)
5822 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5823 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5824 #define CAN_F11R2_FB3_Pos (3U)
5825 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5826 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5827 #define CAN_F11R2_FB4_Pos (4U)
5828 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5829 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5830 #define CAN_F11R2_FB5_Pos (5U)
5831 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5832 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5833 #define CAN_F11R2_FB6_Pos (6U)
5834 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5835 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5836 #define CAN_F11R2_FB7_Pos (7U)
5837 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5838 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5839 #define CAN_F11R2_FB8_Pos (8U)
5840 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5841 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5842 #define CAN_F11R2_FB9_Pos (9U)
5843 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5844 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5845 #define CAN_F11R2_FB10_Pos (10U)
5846 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5847 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5848 #define CAN_F11R2_FB11_Pos (11U)
5849 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5850 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5851 #define CAN_F11R2_FB12_Pos (12U)
5852 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5853 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5854 #define CAN_F11R2_FB13_Pos (13U)
5855 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5856 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5857 #define CAN_F11R2_FB14_Pos (14U)
5858 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5859 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5860 #define CAN_F11R2_FB15_Pos (15U)
5861 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5862 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5863 #define CAN_F11R2_FB16_Pos (16U)
5864 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5865 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5866 #define CAN_F11R2_FB17_Pos (17U)
5867 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5868 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5869 #define CAN_F11R2_FB18_Pos (18U)
5870 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5871 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5872 #define CAN_F11R2_FB19_Pos (19U)
5873 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5874 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5875 #define CAN_F11R2_FB20_Pos (20U)
5876 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5877 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5878 #define CAN_F11R2_FB21_Pos (21U)
5879 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5880 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5881 #define CAN_F11R2_FB22_Pos (22U)
5882 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5883 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5884 #define CAN_F11R2_FB23_Pos (23U)
5885 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5886 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5887 #define CAN_F11R2_FB24_Pos (24U)
5888 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5889 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5890 #define CAN_F11R2_FB25_Pos (25U)
5891 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5892 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5893 #define CAN_F11R2_FB26_Pos (26U)
5894 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5895 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5896 #define CAN_F11R2_FB27_Pos (27U)
5897 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5898 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5899 #define CAN_F11R2_FB28_Pos (28U)
5900 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5901 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5902 #define CAN_F11R2_FB29_Pos (29U)
5903 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5904 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5905 #define CAN_F11R2_FB30_Pos (30U)
5906 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5907 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5908 #define CAN_F11R2_FB31_Pos (31U)
5909 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5910 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5912 /******************* Bit definition for CAN_F12R2 register ******************/
5913 #define CAN_F12R2_FB0_Pos (0U)
5914 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5915 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5916 #define CAN_F12R2_FB1_Pos (1U)
5917 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5918 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5919 #define CAN_F12R2_FB2_Pos (2U)
5920 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5921 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5922 #define CAN_F12R2_FB3_Pos (3U)
5923 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5924 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5925 #define CAN_F12R2_FB4_Pos (4U)
5926 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5927 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5928 #define CAN_F12R2_FB5_Pos (5U)
5929 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5930 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5931 #define CAN_F12R2_FB6_Pos (6U)
5932 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5933 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5934 #define CAN_F12R2_FB7_Pos (7U)
5935 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5936 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5937 #define CAN_F12R2_FB8_Pos (8U)
5938 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5939 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5940 #define CAN_F12R2_FB9_Pos (9U)
5941 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5942 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5943 #define CAN_F12R2_FB10_Pos (10U)
5944 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5945 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5946 #define CAN_F12R2_FB11_Pos (11U)
5947 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5948 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5949 #define CAN_F12R2_FB12_Pos (12U)
5950 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5951 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5952 #define CAN_F12R2_FB13_Pos (13U)
5953 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5954 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5955 #define CAN_F12R2_FB14_Pos (14U)
5956 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5957 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5958 #define CAN_F12R2_FB15_Pos (15U)
5959 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5960 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5961 #define CAN_F12R2_FB16_Pos (16U)
5962 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5963 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5964 #define CAN_F12R2_FB17_Pos (17U)
5965 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5966 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5967 #define CAN_F12R2_FB18_Pos (18U)
5968 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5969 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5970 #define CAN_F12R2_FB19_Pos (19U)
5971 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5972 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5973 #define CAN_F12R2_FB20_Pos (20U)
5974 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5975 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5976 #define CAN_F12R2_FB21_Pos (21U)
5977 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5978 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5979 #define CAN_F12R2_FB22_Pos (22U)
5980 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5981 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5982 #define CAN_F12R2_FB23_Pos (23U)
5983 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5984 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5985 #define CAN_F12R2_FB24_Pos (24U)
5986 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5987 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5988 #define CAN_F12R2_FB25_Pos (25U)
5989 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5990 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5991 #define CAN_F12R2_FB26_Pos (26U)
5992 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5993 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5994 #define CAN_F12R2_FB27_Pos (27U)
5995 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5996 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5997 #define CAN_F12R2_FB28_Pos (28U)
5998 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5999 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
6000 #define CAN_F12R2_FB29_Pos (29U)
6001 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
6002 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
6003 #define CAN_F12R2_FB30_Pos (30U)
6004 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
6005 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
6006 #define CAN_F12R2_FB31_Pos (31U)
6007 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
6008 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
6010 /******************* Bit definition for CAN_F13R2 register ******************/
6011 #define CAN_F13R2_FB0_Pos (0U)
6012 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
6013 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
6014 #define CAN_F13R2_FB1_Pos (1U)
6015 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
6016 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
6017 #define CAN_F13R2_FB2_Pos (2U)
6018 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
6019 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
6020 #define CAN_F13R2_FB3_Pos (3U)
6021 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
6022 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
6023 #define CAN_F13R2_FB4_Pos (4U)
6024 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
6025 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
6026 #define CAN_F13R2_FB5_Pos (5U)
6027 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
6028 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
6029 #define CAN_F13R2_FB6_Pos (6U)
6030 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
6031 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
6032 #define CAN_F13R2_FB7_Pos (7U)
6033 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
6034 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
6035 #define CAN_F13R2_FB8_Pos (8U)
6036 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
6037 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
6038 #define CAN_F13R2_FB9_Pos (9U)
6039 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
6040 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
6041 #define CAN_F13R2_FB10_Pos (10U)
6042 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
6043 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
6044 #define CAN_F13R2_FB11_Pos (11U)
6045 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
6046 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
6047 #define CAN_F13R2_FB12_Pos (12U)
6048 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
6049 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
6050 #define CAN_F13R2_FB13_Pos (13U)
6051 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
6052 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
6053 #define CAN_F13R2_FB14_Pos (14U)
6054 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
6055 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
6056 #define CAN_F13R2_FB15_Pos (15U)
6057 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
6058 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
6059 #define CAN_F13R2_FB16_Pos (16U)
6060 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
6061 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
6062 #define CAN_F13R2_FB17_Pos (17U)
6063 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
6064 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
6065 #define CAN_F13R2_FB18_Pos (18U)
6066 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
6067 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
6068 #define CAN_F13R2_FB19_Pos (19U)
6069 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
6070 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
6071 #define CAN_F13R2_FB20_Pos (20U)
6072 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
6073 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
6074 #define CAN_F13R2_FB21_Pos (21U)
6075 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
6076 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
6077 #define CAN_F13R2_FB22_Pos (22U)
6078 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
6079 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
6080 #define CAN_F13R2_FB23_Pos (23U)
6081 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
6082 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
6083 #define CAN_F13R2_FB24_Pos (24U)
6084 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
6085 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
6086 #define CAN_F13R2_FB25_Pos (25U)
6087 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
6088 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
6089 #define CAN_F13R2_FB26_Pos (26U)
6090 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
6091 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
6092 #define CAN_F13R2_FB27_Pos (27U)
6093 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
6094 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
6095 #define CAN_F13R2_FB28_Pos (28U)
6096 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
6097 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
6098 #define CAN_F13R2_FB29_Pos (29U)
6099 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
6100 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
6101 #define CAN_F13R2_FB30_Pos (30U)
6102 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
6103 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
6104 #define CAN_F13R2_FB31_Pos (31U)
6105 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
6106 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
6108 /******************************************************************************/
6109 /* */
6110 /* CRC calculation unit */
6111 /* */
6112 /******************************************************************************/
6113 /******************* Bit definition for CRC_DR register *********************/
6114 #define CRC_DR_DR_Pos (0U)
6115 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
6116 #define CRC_DR_DR CRC_DR_DR_Msk
6118 /******************* Bit definition for CRC_IDR register ********************/
6119 #define CRC_IDR_IDR_Pos (0U)
6120 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos)
6121 #define CRC_IDR_IDR CRC_IDR_IDR_Msk
6123 /******************** Bit definition for CRC_CR register ********************/
6124 #define CRC_CR_RESET_Pos (0U)
6125 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
6126 #define CRC_CR_RESET CRC_CR_RESET_Msk
6127 #define CRC_CR_POLYSIZE_Pos (3U)
6128 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
6129 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
6130 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
6131 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
6132 #define CRC_CR_REV_IN_Pos (5U)
6133 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
6134 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
6135 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
6136 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
6137 #define CRC_CR_REV_OUT_Pos (7U)
6138 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
6139 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
6141 /******************* Bit definition for CRC_INIT register *******************/
6142 #define CRC_INIT_INIT_Pos (0U)
6143 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
6144 #define CRC_INIT_INIT CRC_INIT_INIT_Msk
6146 /******************* Bit definition for CRC_POL register ********************/
6147 #define CRC_POL_POL_Pos (0U)
6148 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
6149 #define CRC_POL_POL CRC_POL_POL_Msk
6151 /******************************************************************************/
6152 /* */
6153 /* Digital to Analog Converter */
6154 /* */
6155 /******************************************************************************/
6156 /*
6157  * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
6158  */
6159 #define DAC_CHANNEL2_SUPPORT
6161 /******************** Bit definition for DAC_CR register ********************/
6162 #define DAC_CR_EN1_Pos (0U)
6163 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
6164 #define DAC_CR_EN1 DAC_CR_EN1_Msk
6165 #define DAC_CR_TEN1_Pos (2U)
6166 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
6167 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk
6169 #define DAC_CR_TSEL1_Pos (3U)
6170 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
6171 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
6172 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
6173 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
6174 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
6176 #define DAC_CR_WAVE1_Pos (6U)
6177 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
6178 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
6179 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
6180 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
6182 #define DAC_CR_MAMP1_Pos (8U)
6183 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
6184 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
6185 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
6186 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
6187 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
6188 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
6190 #define DAC_CR_DMAEN1_Pos (12U)
6191 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
6192 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
6193 #define DAC_CR_DMAUDRIE1_Pos (13U)
6194 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
6195 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
6196 #define DAC_CR_CEN1_Pos (14U)
6197 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
6198 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk
6200 #define DAC_CR_EN2_Pos (16U)
6201 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
6202 #define DAC_CR_EN2 DAC_CR_EN2_Msk
6203 #define DAC_CR_TEN2_Pos (18U)
6204 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
6205 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk
6207 #define DAC_CR_TSEL2_Pos (19U)
6208 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
6209 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
6210 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
6211 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
6212 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
6214 #define DAC_CR_WAVE2_Pos (22U)
6215 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
6216 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
6217 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
6218 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
6220 #define DAC_CR_MAMP2_Pos (24U)
6221 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
6222 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
6223 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
6224 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
6225 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
6226 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
6228 #define DAC_CR_DMAEN2_Pos (28U)
6229 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
6230 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
6231 #define DAC_CR_DMAUDRIE2_Pos (29U)
6232 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
6233 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
6234 #define DAC_CR_CEN2_Pos (30U)
6235 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
6236 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk
6238 /***************** Bit definition for DAC_SWTRIGR register ******************/
6239 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6240 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
6241 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
6242 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6243 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
6244 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
6246 /***************** Bit definition for DAC_DHR12R1 register ******************/
6247 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
6248 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
6249 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
6251 /***************** Bit definition for DAC_DHR12L1 register ******************/
6252 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
6253 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
6254 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
6256 /****************** Bit definition for DAC_DHR8R1 register ******************/
6257 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
6258 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
6259 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
6261 /***************** Bit definition for DAC_DHR12R2 register ******************/
6262 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
6263 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
6264 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
6266 /***************** Bit definition for DAC_DHR12L2 register ******************/
6267 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
6268 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
6269 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
6271 /****************** Bit definition for DAC_DHR8R2 register ******************/
6272 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
6273 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
6274 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
6276 /***************** Bit definition for DAC_DHR12RD register ******************/
6277 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
6278 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6279 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6280 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
6281 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6282 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6284 /***************** Bit definition for DAC_DHR12LD register ******************/
6285 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
6286 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6287 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6288 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
6289 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6290 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6292 /****************** Bit definition for DAC_DHR8RD register ******************/
6293 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
6294 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6295 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6296 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
6297 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6298 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6300 /******************* Bit definition for DAC_DOR1 register *******************/
6301 #define DAC_DOR1_DACC1DOR_Pos (0U)
6302 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6303 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6305 /******************* Bit definition for DAC_DOR2 register *******************/
6306 #define DAC_DOR2_DACC2DOR_Pos (0U)
6307 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6308 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6310 /******************** Bit definition for DAC_SR register ********************/
6311 #define DAC_SR_DMAUDR1_Pos (13U)
6312 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6313 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6314 #define DAC_SR_CAL_FLAG1_Pos (14U)
6315 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
6316 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
6317 #define DAC_SR_BWST1_Pos (15U)
6318 #define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos)
6319 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk
6321 #define DAC_SR_DMAUDR2_Pos (29U)
6322 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6323 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6324 #define DAC_SR_CAL_FLAG2_Pos (30U)
6325 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
6326 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
6327 #define DAC_SR_BWST2_Pos (31U)
6328 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
6329 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk
6331 /******************* Bit definition for DAC_CCR register ********************/
6332 #define DAC_CCR_OTRIM1_Pos (0U)
6333 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
6334 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
6335 #define DAC_CCR_OTRIM2_Pos (16U)
6336 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
6337 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
6339 /******************* Bit definition for DAC_MCR register *******************/
6340 #define DAC_MCR_MODE1_Pos (0U)
6341 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6342 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6343 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6344 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6345 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6347 #define DAC_MCR_MODE2_Pos (16U)
6348 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6349 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6350 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6351 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6352 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6354 /****************** Bit definition for DAC_SHSR1 register ******************/
6355 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
6356 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6357 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6359 /****************** Bit definition for DAC_SHSR2 register ******************/
6360 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
6361 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6362 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6364 /****************** Bit definition for DAC_SHHR register ******************/
6365 #define DAC_SHHR_THOLD1_Pos (0U)
6366 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6367 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6368 #define DAC_SHHR_THOLD2_Pos (16U)
6369 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6370 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6372 /****************** Bit definition for DAC_SHRR register ******************/
6373 #define DAC_SHRR_TREFRESH1_Pos (0U)
6374 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6375 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6376 #define DAC_SHRR_TREFRESH2_Pos (16U)
6377 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6378 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6380 /******************************************************************************/
6381 /* */
6382 /* Digital Filter for Sigma Delta Modulators */
6383 /* */
6384 /******************************************************************************/
6385 
6386 /**************** DFSDM channel configuration registers ********************/
6387 
6388 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6389 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6390 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6391 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6392 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6393 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6394 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6395 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6396 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6397 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6398 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6399 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6400 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6401 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6402 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6403 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6404 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6405 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6406 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6407 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6408 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6409 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6410 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6411 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
6412 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6413 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6414 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6415 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6416 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6417 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6418 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6419 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6420 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6421 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6422 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6423 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6424 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6425 #define DFSDM_CHCFGR1_SITP_Pos (0U)
6426 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6427 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6428 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6429 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6431 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6432 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6433 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6434 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6435 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6436 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6437 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6439 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
6440 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6441 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6442 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6443 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6444 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6445 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6446 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6447 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6448 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6449 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6450 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6451 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6452 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6453 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6455 /**************** Bit definition for DFSDM_CHWDATR register *******************/
6456 #define DFSDM_CHWDATR_WDATA_Pos (0U)
6457 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6458 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6460 /**************** Bit definition for DFSDM_CHDATINR register *****************/
6461 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
6462 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6463 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6464 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
6465 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6466 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6468 /************************ DFSDM module registers ****************************/
6469 
6470 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
6471 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6472 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6473 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6474 #define DFSDM_FLTCR1_FAST_Pos (29U)
6475 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6476 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6477 #define DFSDM_FLTCR1_RCH_Pos (24U)
6478 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6479 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6480 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6481 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6482 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6483 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6484 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6485 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6486 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6487 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6488 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6489 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6490 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6491 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6492 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6493 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6494 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6495 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6496 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6497 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6498 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6499 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6500 #define DFSDM_FLTCR1_JEXTSEL_2 (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6501 #define DFSDM_FLTCR1_JEXTSEL_1 (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6502 #define DFSDM_FLTCR1_JEXTSEL_0 (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6503 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6504 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6505 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6506 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6507 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6508 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6509 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6510 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6511 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6512 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6513 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6514 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6515 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6516 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6517 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6519 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
6520 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6521 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6522 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6523 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6524 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6525 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6526 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6527 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6528 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6529 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6530 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6531 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6532 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6533 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6534 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6535 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6536 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6537 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6538 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6539 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6540 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6541 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6542 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6543 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6544 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6545 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6546 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6548 /***************** Bit definition for DFSDM_FLTISR register *******************/
6549 #define DFSDM_FLTISR_SCDF_Pos (24U)
6550 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6551 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6552 #define DFSDM_FLTISR_CKABF_Pos (16U)
6553 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6554 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6555 #define DFSDM_FLTISR_RCIP_Pos (14U)
6556 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6557 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6558 #define DFSDM_FLTISR_JCIP_Pos (13U)
6559 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6560 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6561 #define DFSDM_FLTISR_AWDF_Pos (4U)
6562 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6563 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6564 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6565 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6566 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6567 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6568 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6569 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6570 #define DFSDM_FLTISR_REOCF_Pos (1U)
6571 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6572 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6573 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6574 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6575 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6577 /***************** Bit definition for DFSDM_FLTICR register *******************/
6578 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6579 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6580 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6581 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6582 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6583 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6584 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6585 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6586 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6587 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6588 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6589 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6591 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
6592 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6593 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6594 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6596 /***************** Bit definition for DFSDM_FLTFCR register *******************/
6597 #define DFSDM_FLTFCR_FORD_Pos (29U)
6598 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6599 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6600 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6601 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6602 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6603 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6604 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6605 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6606 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6607 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6608 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6610 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
6611 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6612 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6613 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6614 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6615 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6616 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6618 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
6619 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6620 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6621 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6622 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6623 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6624 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6625 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6626 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6627 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6629 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
6630 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6631 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6632 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6633 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6634 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6635 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6637 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
6638 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6639 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6640 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6641 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6642 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6643 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6645 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
6646 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6647 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6648 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6649 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6650 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6651 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6653 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
6654 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6655 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6656 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6657 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6658 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6659 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6661 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
6662 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6663 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6664 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6665 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6666 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6667 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6669 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
6670 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6671 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6672 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6673 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6674 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6675 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6677 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
6678 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6679 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6680 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6682 /******************************************************************************/
6683 /* */
6684 /* DMA Controller (DMA) */
6685 /* */
6686 /******************************************************************************/
6687 
6688 /******************* Bit definition for DMA_ISR register ********************/
6689 #define DMA_ISR_GIF1_Pos (0U)
6690 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
6691 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
6692 #define DMA_ISR_TCIF1_Pos (1U)
6693 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
6694 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
6695 #define DMA_ISR_HTIF1_Pos (2U)
6696 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
6697 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
6698 #define DMA_ISR_TEIF1_Pos (3U)
6699 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
6700 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
6701 #define DMA_ISR_GIF2_Pos (4U)
6702 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
6703 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
6704 #define DMA_ISR_TCIF2_Pos (5U)
6705 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
6706 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
6707 #define DMA_ISR_HTIF2_Pos (6U)
6708 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
6709 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
6710 #define DMA_ISR_TEIF2_Pos (7U)
6711 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
6712 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
6713 #define DMA_ISR_GIF3_Pos (8U)
6714 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
6715 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
6716 #define DMA_ISR_TCIF3_Pos (9U)
6717 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
6718 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
6719 #define DMA_ISR_HTIF3_Pos (10U)
6720 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
6721 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
6722 #define DMA_ISR_TEIF3_Pos (11U)
6723 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
6724 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
6725 #define DMA_ISR_GIF4_Pos (12U)
6726 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
6727 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
6728 #define DMA_ISR_TCIF4_Pos (13U)
6729 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
6730 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
6731 #define DMA_ISR_HTIF4_Pos (14U)
6732 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
6733 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
6734 #define DMA_ISR_TEIF4_Pos (15U)
6735 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
6736 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
6737 #define DMA_ISR_GIF5_Pos (16U)
6738 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
6739 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
6740 #define DMA_ISR_TCIF5_Pos (17U)
6741 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
6742 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
6743 #define DMA_ISR_HTIF5_Pos (18U)
6744 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
6745 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
6746 #define DMA_ISR_TEIF5_Pos (19U)
6747 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
6748 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
6749 #define DMA_ISR_GIF6_Pos (20U)
6750 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
6751 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
6752 #define DMA_ISR_TCIF6_Pos (21U)
6753 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
6754 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
6755 #define DMA_ISR_HTIF6_Pos (22U)
6756 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
6757 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
6758 #define DMA_ISR_TEIF6_Pos (23U)
6759 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
6760 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
6761 #define DMA_ISR_GIF7_Pos (24U)
6762 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
6763 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
6764 #define DMA_ISR_TCIF7_Pos (25U)
6765 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
6766 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
6767 #define DMA_ISR_HTIF7_Pos (26U)
6768 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
6769 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
6770 #define DMA_ISR_TEIF7_Pos (27U)
6771 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
6772 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
6774 /******************* Bit definition for DMA_IFCR register *******************/
6775 #define DMA_IFCR_CGIF1_Pos (0U)
6776 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
6777 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
6778 #define DMA_IFCR_CTCIF1_Pos (1U)
6779 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
6780 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
6781 #define DMA_IFCR_CHTIF1_Pos (2U)
6782 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
6783 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
6784 #define DMA_IFCR_CTEIF1_Pos (3U)
6785 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
6786 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
6787 #define DMA_IFCR_CGIF2_Pos (4U)
6788 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
6789 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
6790 #define DMA_IFCR_CTCIF2_Pos (5U)
6791 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
6792 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
6793 #define DMA_IFCR_CHTIF2_Pos (6U)
6794 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
6795 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
6796 #define DMA_IFCR_CTEIF2_Pos (7U)
6797 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
6798 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
6799 #define DMA_IFCR_CGIF3_Pos (8U)
6800 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
6801 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
6802 #define DMA_IFCR_CTCIF3_Pos (9U)
6803 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
6804 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
6805 #define DMA_IFCR_CHTIF3_Pos (10U)
6806 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
6807 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
6808 #define DMA_IFCR_CTEIF3_Pos (11U)
6809 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
6810 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
6811 #define DMA_IFCR_CGIF4_Pos (12U)
6812 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
6813 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
6814 #define DMA_IFCR_CTCIF4_Pos (13U)
6815 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
6816 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
6817 #define DMA_IFCR_CHTIF4_Pos (14U)
6818 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
6819 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
6820 #define DMA_IFCR_CTEIF4_Pos (15U)
6821 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
6822 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
6823 #define DMA_IFCR_CGIF5_Pos (16U)
6824 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
6825 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
6826 #define DMA_IFCR_CTCIF5_Pos (17U)
6827 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
6828 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
6829 #define DMA_IFCR_CHTIF5_Pos (18U)
6830 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
6831 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
6832 #define DMA_IFCR_CTEIF5_Pos (19U)
6833 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
6834 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
6835 #define DMA_IFCR_CGIF6_Pos (20U)
6836 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
6837 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
6838 #define DMA_IFCR_CTCIF6_Pos (21U)
6839 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
6840 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
6841 #define DMA_IFCR_CHTIF6_Pos (22U)
6842 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
6843 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
6844 #define DMA_IFCR_CTEIF6_Pos (23U)
6845 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
6846 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
6847 #define DMA_IFCR_CGIF7_Pos (24U)
6848 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
6849 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
6850 #define DMA_IFCR_CTCIF7_Pos (25U)
6851 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
6852 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
6853 #define DMA_IFCR_CHTIF7_Pos (26U)
6854 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
6855 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
6856 #define DMA_IFCR_CTEIF7_Pos (27U)
6857 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
6858 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
6860 /******************* Bit definition for DMA_CCR register ********************/
6861 #define DMA_CCR_EN_Pos (0U)
6862 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
6863 #define DMA_CCR_EN DMA_CCR_EN_Msk
6864 #define DMA_CCR_TCIE_Pos (1U)
6865 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
6866 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
6867 #define DMA_CCR_HTIE_Pos (2U)
6868 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
6869 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
6870 #define DMA_CCR_TEIE_Pos (3U)
6871 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
6872 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
6873 #define DMA_CCR_DIR_Pos (4U)
6874 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
6875 #define DMA_CCR_DIR DMA_CCR_DIR_Msk
6876 #define DMA_CCR_CIRC_Pos (5U)
6877 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
6878 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
6879 #define DMA_CCR_PINC_Pos (6U)
6880 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
6881 #define DMA_CCR_PINC DMA_CCR_PINC_Msk
6882 #define DMA_CCR_MINC_Pos (7U)
6883 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
6884 #define DMA_CCR_MINC DMA_CCR_MINC_Msk
6886 #define DMA_CCR_PSIZE_Pos (8U)
6887 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
6888 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
6889 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
6890 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
6892 #define DMA_CCR_MSIZE_Pos (10U)
6893 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
6894 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
6895 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
6896 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
6898 #define DMA_CCR_PL_Pos (12U)
6899 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
6900 #define DMA_CCR_PL DMA_CCR_PL_Msk
6901 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
6902 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
6904 #define DMA_CCR_MEM2MEM_Pos (14U)
6905 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
6906 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
6908 /****************** Bit definition for DMA_CNDTR register *******************/
6909 #define DMA_CNDTR_NDT_Pos (0U)
6910 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
6911 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
6913 /****************** Bit definition for DMA_CPAR register ********************/
6914 #define DMA_CPAR_PA_Pos (0U)
6915 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
6916 #define DMA_CPAR_PA DMA_CPAR_PA_Msk
6918 /****************** Bit definition for DMA_CMAR register ********************/
6919 #define DMA_CMAR_MA_Pos (0U)
6920 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
6921 #define DMA_CMAR_MA DMA_CMAR_MA_Msk
6924 /******************* Bit definition for DMA_CSELR register *******************/
6925 #define DMA_CSELR_C1S_Pos (0U)
6926 #define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos)
6927 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk
6928 #define DMA_CSELR_C2S_Pos (4U)
6929 #define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos)
6930 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk
6931 #define DMA_CSELR_C3S_Pos (8U)
6932 #define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos)
6933 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk
6934 #define DMA_CSELR_C4S_Pos (12U)
6935 #define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos)
6936 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk
6937 #define DMA_CSELR_C5S_Pos (16U)
6938 #define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos)
6939 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk
6940 #define DMA_CSELR_C6S_Pos (20U)
6941 #define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos)
6942 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk
6943 #define DMA_CSELR_C7S_Pos (24U)
6944 #define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos)
6945 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk
6947 /******************************************************************************/
6948 /* */
6949 /* External Interrupt/Event Controller */
6950 /* */
6951 /******************************************************************************/
6952 /******************* Bit definition for EXTI_IMR1 register ******************/
6953 #define EXTI_IMR1_IM0_Pos (0U)
6954 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
6955 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
6956 #define EXTI_IMR1_IM1_Pos (1U)
6957 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
6958 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
6959 #define EXTI_IMR1_IM2_Pos (2U)
6960 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
6961 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
6962 #define EXTI_IMR1_IM3_Pos (3U)
6963 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
6964 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
6965 #define EXTI_IMR1_IM4_Pos (4U)
6966 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
6967 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
6968 #define EXTI_IMR1_IM5_Pos (5U)
6969 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
6970 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
6971 #define EXTI_IMR1_IM6_Pos (6U)
6972 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
6973 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
6974 #define EXTI_IMR1_IM7_Pos (7U)
6975 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
6976 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
6977 #define EXTI_IMR1_IM8_Pos (8U)
6978 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
6979 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
6980 #define EXTI_IMR1_IM9_Pos (9U)
6981 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
6982 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
6983 #define EXTI_IMR1_IM10_Pos (10U)
6984 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
6985 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
6986 #define EXTI_IMR1_IM11_Pos (11U)
6987 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
6988 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
6989 #define EXTI_IMR1_IM12_Pos (12U)
6990 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
6991 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
6992 #define EXTI_IMR1_IM13_Pos (13U)
6993 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
6994 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
6995 #define EXTI_IMR1_IM14_Pos (14U)
6996 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
6997 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
6998 #define EXTI_IMR1_IM15_Pos (15U)
6999 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
7000 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
7001 #define EXTI_IMR1_IM16_Pos (16U)
7002 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
7003 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
7004 #define EXTI_IMR1_IM17_Pos (17U)
7005 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
7006 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
7007 #define EXTI_IMR1_IM18_Pos (18U)
7008 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
7009 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
7010 #define EXTI_IMR1_IM19_Pos (19U)
7011 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
7012 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
7013 #define EXTI_IMR1_IM20_Pos (20U)
7014 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
7015 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
7016 #define EXTI_IMR1_IM21_Pos (21U)
7017 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
7018 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
7019 #define EXTI_IMR1_IM22_Pos (22U)
7020 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
7021 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
7022 #define EXTI_IMR1_IM23_Pos (23U)
7023 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
7024 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
7025 #define EXTI_IMR1_IM24_Pos (24U)
7026 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
7027 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
7028 #define EXTI_IMR1_IM25_Pos (25U)
7029 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
7030 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
7031 #define EXTI_IMR1_IM26_Pos (26U)
7032 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
7033 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
7034 #define EXTI_IMR1_IM27_Pos (27U)
7035 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
7036 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
7037 #define EXTI_IMR1_IM28_Pos (28U)
7038 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
7039 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
7040 #define EXTI_IMR1_IM29_Pos (29U)
7041 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
7042 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
7043 #define EXTI_IMR1_IM30_Pos (30U)
7044 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
7045 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
7046 #define EXTI_IMR1_IM31_Pos (31U)
7047 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
7048 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
7049 #define EXTI_IMR1_IM_Pos (0U)
7050 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
7051 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
7053 /******************* Bit definition for EXTI_EMR1 register ******************/
7054 #define EXTI_EMR1_EM0_Pos (0U)
7055 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
7056 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
7057 #define EXTI_EMR1_EM1_Pos (1U)
7058 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
7059 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
7060 #define EXTI_EMR1_EM2_Pos (2U)
7061 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
7062 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
7063 #define EXTI_EMR1_EM3_Pos (3U)
7064 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
7065 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
7066 #define EXTI_EMR1_EM4_Pos (4U)
7067 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
7068 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
7069 #define EXTI_EMR1_EM5_Pos (5U)
7070 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
7071 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
7072 #define EXTI_EMR1_EM6_Pos (6U)
7073 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
7074 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
7075 #define EXTI_EMR1_EM7_Pos (7U)
7076 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
7077 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
7078 #define EXTI_EMR1_EM8_Pos (8U)
7079 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
7080 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
7081 #define EXTI_EMR1_EM9_Pos (9U)
7082 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
7083 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
7084 #define EXTI_EMR1_EM10_Pos (10U)
7085 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
7086 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
7087 #define EXTI_EMR1_EM11_Pos (11U)
7088 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
7089 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
7090 #define EXTI_EMR1_EM12_Pos (12U)
7091 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
7092 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
7093 #define EXTI_EMR1_EM13_Pos (13U)
7094 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
7095 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
7096 #define EXTI_EMR1_EM14_Pos (14U)
7097 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
7098 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
7099 #define EXTI_EMR1_EM15_Pos (15U)
7100 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
7101 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
7102 #define EXTI_EMR1_EM16_Pos (16U)
7103 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
7104 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
7105 #define EXTI_EMR1_EM17_Pos (17U)
7106 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
7107 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
7108 #define EXTI_EMR1_EM18_Pos (18U)
7109 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
7110 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
7111 #define EXTI_EMR1_EM19_Pos (19U)
7112 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)
7113 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk
7114 #define EXTI_EMR1_EM20_Pos (20U)
7115 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
7116 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
7117 #define EXTI_EMR1_EM21_Pos (21U)
7118 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
7119 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
7120 #define EXTI_EMR1_EM22_Pos (22U)
7121 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
7122 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
7123 #define EXTI_EMR1_EM23_Pos (23U)
7124 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
7125 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
7126 #define EXTI_EMR1_EM24_Pos (24U)
7127 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
7128 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
7129 #define EXTI_EMR1_EM25_Pos (25U)
7130 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
7131 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
7132 #define EXTI_EMR1_EM26_Pos (26U)
7133 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
7134 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
7135 #define EXTI_EMR1_EM27_Pos (27U)
7136 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
7137 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
7138 #define EXTI_EMR1_EM28_Pos (28U)
7139 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
7140 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
7141 #define EXTI_EMR1_EM29_Pos (29U)
7142 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
7143 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
7144 #define EXTI_EMR1_EM30_Pos (30U)
7145 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
7146 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
7147 #define EXTI_EMR1_EM31_Pos (31U)
7148 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
7149 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
7151 /****************** Bit definition for EXTI_RTSR1 register ******************/
7152 #define EXTI_RTSR1_RT0_Pos (0U)
7153 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)
7154 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk
7155 #define EXTI_RTSR1_RT1_Pos (1U)
7156 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)
7157 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk
7158 #define EXTI_RTSR1_RT2_Pos (2U)
7159 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)
7160 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk
7161 #define EXTI_RTSR1_RT3_Pos (3U)
7162 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)
7163 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk
7164 #define EXTI_RTSR1_RT4_Pos (4U)
7165 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)
7166 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk
7167 #define EXTI_RTSR1_RT5_Pos (5U)
7168 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)
7169 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk
7170 #define EXTI_RTSR1_RT6_Pos (6U)
7171 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)
7172 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk
7173 #define EXTI_RTSR1_RT7_Pos (7U)
7174 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)
7175 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk
7176 #define EXTI_RTSR1_RT8_Pos (8U)
7177 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)
7178 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk
7179 #define EXTI_RTSR1_RT9_Pos (9U)
7180 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)
7181 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk
7182 #define EXTI_RTSR1_RT10_Pos (10U)
7183 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)
7184 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk
7185 #define EXTI_RTSR1_RT11_Pos (11U)
7186 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)
7187 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk
7188 #define EXTI_RTSR1_RT12_Pos (12U)
7189 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)
7190 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk
7191 #define EXTI_RTSR1_RT13_Pos (13U)
7192 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)
7193 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk
7194 #define EXTI_RTSR1_RT14_Pos (14U)
7195 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)
7196 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk
7197 #define EXTI_RTSR1_RT15_Pos (15U)
7198 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)
7199 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk
7200 #define EXTI_RTSR1_RT16_Pos (16U)
7201 #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos)
7202 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk
7203 #define EXTI_RTSR1_RT18_Pos (18U)
7204 #define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos)
7205 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk
7206 #define EXTI_RTSR1_RT19_Pos (19U)
7207 #define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos)
7208 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk
7209 #define EXTI_RTSR1_RT20_Pos (20U)
7210 #define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos)
7211 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk
7212 #define EXTI_RTSR1_RT21_Pos (21U)
7213 #define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos)
7214 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk
7215 #define EXTI_RTSR1_RT22_Pos (22U)
7216 #define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos)
7217 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk
7219 /****************** Bit definition for EXTI_FTSR1 register ******************/
7220 #define EXTI_FTSR1_FT0_Pos (0U)
7221 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)
7222 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk
7223 #define EXTI_FTSR1_FT1_Pos (1U)
7224 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)
7225 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk
7226 #define EXTI_FTSR1_FT2_Pos (2U)
7227 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)
7228 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk
7229 #define EXTI_FTSR1_FT3_Pos (3U)
7230 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)
7231 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk
7232 #define EXTI_FTSR1_FT4_Pos (4U)
7233 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)
7234 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk
7235 #define EXTI_FTSR1_FT5_Pos (5U)
7236 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)
7237 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk
7238 #define EXTI_FTSR1_FT6_Pos (6U)
7239 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)
7240 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk
7241 #define EXTI_FTSR1_FT7_Pos (7U)
7242 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)
7243 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk
7244 #define EXTI_FTSR1_FT8_Pos (8U)
7245 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)
7246 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk
7247 #define EXTI_FTSR1_FT9_Pos (9U)
7248 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)
7249 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk
7250 #define EXTI_FTSR1_FT10_Pos (10U)
7251 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)
7252 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk
7253 #define EXTI_FTSR1_FT11_Pos (11U)
7254 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)
7255 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk
7256 #define EXTI_FTSR1_FT12_Pos (12U)
7257 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)
7258 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk
7259 #define EXTI_FTSR1_FT13_Pos (13U)
7260 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)
7261 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk
7262 #define EXTI_FTSR1_FT14_Pos (14U)
7263 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)
7264 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk
7265 #define EXTI_FTSR1_FT15_Pos (15U)
7266 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)
7267 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk
7268 #define EXTI_FTSR1_FT16_Pos (16U)
7269 #define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos)
7270 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk
7271 #define EXTI_FTSR1_FT18_Pos (18U)
7272 #define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos)
7273 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk
7274 #define EXTI_FTSR1_FT19_Pos (19U)
7275 #define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos)
7276 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk
7277 #define EXTI_FTSR1_FT20_Pos (20U)
7278 #define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos)
7279 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk
7280 #define EXTI_FTSR1_FT21_Pos (21U)
7281 #define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos)
7282 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk
7283 #define EXTI_FTSR1_FT22_Pos (22U)
7284 #define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos)
7285 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk
7287 /****************** Bit definition for EXTI_SWIER1 register *****************/
7288 #define EXTI_SWIER1_SWI0_Pos (0U)
7289 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)
7290 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk
7291 #define EXTI_SWIER1_SWI1_Pos (1U)
7292 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)
7293 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk
7294 #define EXTI_SWIER1_SWI2_Pos (2U)
7295 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)
7296 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk
7297 #define EXTI_SWIER1_SWI3_Pos (3U)
7298 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)
7299 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk
7300 #define EXTI_SWIER1_SWI4_Pos (4U)
7301 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)
7302 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk
7303 #define EXTI_SWIER1_SWI5_Pos (5U)
7304 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)
7305 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk
7306 #define EXTI_SWIER1_SWI6_Pos (6U)
7307 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)
7308 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk
7309 #define EXTI_SWIER1_SWI7_Pos (7U)
7310 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)
7311 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk
7312 #define EXTI_SWIER1_SWI8_Pos (8U)
7313 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)
7314 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk
7315 #define EXTI_SWIER1_SWI9_Pos (9U)
7316 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)
7317 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk
7318 #define EXTI_SWIER1_SWI10_Pos (10U)
7319 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)
7320 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk
7321 #define EXTI_SWIER1_SWI11_Pos (11U)
7322 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)
7323 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk
7324 #define EXTI_SWIER1_SWI12_Pos (12U)
7325 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)
7326 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk
7327 #define EXTI_SWIER1_SWI13_Pos (13U)
7328 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)
7329 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk
7330 #define EXTI_SWIER1_SWI14_Pos (14U)
7331 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)
7332 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk
7333 #define EXTI_SWIER1_SWI15_Pos (15U)
7334 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)
7335 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk
7336 #define EXTI_SWIER1_SWI16_Pos (16U)
7337 #define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos)
7338 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk
7339 #define EXTI_SWIER1_SWI18_Pos (18U)
7340 #define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos)
7341 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk
7342 #define EXTI_SWIER1_SWI19_Pos (19U)
7343 #define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos)
7344 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk
7345 #define EXTI_SWIER1_SWI20_Pos (20U)
7346 #define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos)
7347 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk
7348 #define EXTI_SWIER1_SWI21_Pos (21U)
7349 #define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos)
7350 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk
7351 #define EXTI_SWIER1_SWI22_Pos (22U)
7352 #define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos)
7353 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk
7355 /******************* Bit definition for EXTI_PR1 register *******************/
7356 #define EXTI_PR1_PIF0_Pos (0U)
7357 #define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos)
7358 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk
7359 #define EXTI_PR1_PIF1_Pos (1U)
7360 #define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos)
7361 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk
7362 #define EXTI_PR1_PIF2_Pos (2U)
7363 #define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos)
7364 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk
7365 #define EXTI_PR1_PIF3_Pos (3U)
7366 #define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos)
7367 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk
7368 #define EXTI_PR1_PIF4_Pos (4U)
7369 #define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos)
7370 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk
7371 #define EXTI_PR1_PIF5_Pos (5U)
7372 #define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos)
7373 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk
7374 #define EXTI_PR1_PIF6_Pos (6U)
7375 #define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos)
7376 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk
7377 #define EXTI_PR1_PIF7_Pos (7U)
7378 #define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos)
7379 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk
7380 #define EXTI_PR1_PIF8_Pos (8U)
7381 #define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos)
7382 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk
7383 #define EXTI_PR1_PIF9_Pos (9U)
7384 #define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos)
7385 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk
7386 #define EXTI_PR1_PIF10_Pos (10U)
7387 #define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos)
7388 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk
7389 #define EXTI_PR1_PIF11_Pos (11U)
7390 #define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos)
7391 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk
7392 #define EXTI_PR1_PIF12_Pos (12U)
7393 #define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos)
7394 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk
7395 #define EXTI_PR1_PIF13_Pos (13U)
7396 #define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos)
7397 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk
7398 #define EXTI_PR1_PIF14_Pos (14U)
7399 #define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos)
7400 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk
7401 #define EXTI_PR1_PIF15_Pos (15U)
7402 #define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos)
7403 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk
7404 #define EXTI_PR1_PIF16_Pos (16U)
7405 #define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos)
7406 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk
7407 #define EXTI_PR1_PIF18_Pos (18U)
7408 #define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos)
7409 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk
7410 #define EXTI_PR1_PIF19_Pos (19U)
7411 #define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos)
7412 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk
7413 #define EXTI_PR1_PIF20_Pos (20U)
7414 #define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos)
7415 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk
7416 #define EXTI_PR1_PIF21_Pos (21U)
7417 #define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos)
7418 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk
7419 #define EXTI_PR1_PIF22_Pos (22U)
7420 #define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos)
7421 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk
7423 /******************* Bit definition for EXTI_IMR2 register ******************/
7424 #define EXTI_IMR2_IM32_Pos (0U)
7425 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
7426 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
7427 #define EXTI_IMR2_IM33_Pos (1U)
7428 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
7429 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
7430 #define EXTI_IMR2_IM34_Pos (2U)
7431 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
7432 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
7433 #define EXTI_IMR2_IM35_Pos (3U)
7434 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
7435 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
7436 #define EXTI_IMR2_IM36_Pos (4U)
7437 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
7438 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
7439 #define EXTI_IMR2_IM37_Pos (5U)
7440 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
7441 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
7442 #define EXTI_IMR2_IM38_Pos (6U)
7443 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
7444 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
7445 #define EXTI_IMR2_IM39_Pos (7U)
7446 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
7447 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
7448 #define EXTI_IMR2_IM_Pos (0U)
7449 #define EXTI_IMR2_IM_Msk (0xFFUL << EXTI_IMR2_IM_Pos)
7450 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7452 /******************* Bit definition for EXTI_EMR2 register ******************/
7453 #define EXTI_EMR2_EM32_Pos (0U)
7454 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
7455 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
7456 #define EXTI_EMR2_EM33_Pos (1U)
7457 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
7458 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
7459 #define EXTI_EMR2_EM34_Pos (2U)
7460 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
7461 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
7462 #define EXTI_EMR2_EM35_Pos (3U)
7463 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
7464 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
7465 #define EXTI_EMR2_EM36_Pos (4U)
7466 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
7467 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
7468 #define EXTI_EMR2_EM37_Pos (5U)
7469 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
7470 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
7471 #define EXTI_EMR2_EM38_Pos (6U)
7472 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
7473 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
7474 #define EXTI_EMR2_EM39_Pos (7U)
7475 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
7476 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
7477 #define EXTI_EMR2_EM_Pos (0U)
7478 #define EXTI_EMR2_EM_Msk (0xFFUL << EXTI_EMR2_EM_Pos)
7479 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
7481 /****************** Bit definition for EXTI_RTSR2 register ******************/
7482 #define EXTI_RTSR2_RT35_Pos (3U)
7483 #define EXTI_RTSR2_RT35_Msk (0x1UL << EXTI_RTSR2_RT35_Pos)
7484 #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk
7485 #define EXTI_RTSR2_RT36_Pos (4U)
7486 #define EXTI_RTSR2_RT36_Msk (0x1UL << EXTI_RTSR2_RT36_Pos)
7487 #define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk
7488 #define EXTI_RTSR2_RT37_Pos (5U)
7489 #define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos)
7490 #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk
7491 #define EXTI_RTSR2_RT38_Pos (6U)
7492 #define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos)
7493 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk
7495 /****************** Bit definition for EXTI_FTSR2 register ******************/
7496 #define EXTI_FTSR2_FT35_Pos (3U)
7497 #define EXTI_FTSR2_FT35_Msk (0x1UL << EXTI_FTSR2_FT35_Pos)
7498 #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk
7499 #define EXTI_FTSR2_FT36_Pos (4U)
7500 #define EXTI_FTSR2_FT36_Msk (0x1UL << EXTI_FTSR2_FT36_Pos)
7501 #define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk
7502 #define EXTI_FTSR2_FT37_Pos (5U)
7503 #define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos)
7504 #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk
7505 #define EXTI_FTSR2_FT38_Pos (6U)
7506 #define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos)
7507 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk
7509 /****************** Bit definition for EXTI_SWIER2 register *****************/
7510 #define EXTI_SWIER2_SWI35_Pos (3U)
7511 #define EXTI_SWIER2_SWI35_Msk (0x1UL << EXTI_SWIER2_SWI35_Pos)
7512 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk
7513 #define EXTI_SWIER2_SWI36_Pos (4U)
7514 #define EXTI_SWIER2_SWI36_Msk (0x1UL << EXTI_SWIER2_SWI36_Pos)
7515 #define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk
7516 #define EXTI_SWIER2_SWI37_Pos (5U)
7517 #define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos)
7518 #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk
7519 #define EXTI_SWIER2_SWI38_Pos (6U)
7520 #define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos)
7521 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk
7523 /******************* Bit definition for EXTI_PR2 register *******************/
7524 #define EXTI_PR2_PIF35_Pos (3U)
7525 #define EXTI_PR2_PIF35_Msk (0x1UL << EXTI_PR2_PIF35_Pos)
7526 #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk
7527 #define EXTI_PR2_PIF36_Pos (4U)
7528 #define EXTI_PR2_PIF36_Msk (0x1UL << EXTI_PR2_PIF36_Pos)
7529 #define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk
7530 #define EXTI_PR2_PIF37_Pos (5U)
7531 #define EXTI_PR2_PIF37_Msk (0x1UL << EXTI_PR2_PIF37_Pos)
7532 #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk
7533 #define EXTI_PR2_PIF38_Pos (6U)
7534 #define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos)
7535 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk
7538 /******************************************************************************/
7539 /* */
7540 /* FLASH */
7541 /* */
7542 /******************************************************************************/
7543 /******************* Bits definition for FLASH_ACR register *****************/
7544 #define FLASH_ACR_LATENCY_Pos (0U)
7545 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
7546 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7547 #define FLASH_ACR_LATENCY_0WS (0x00000000UL)
7548 #define FLASH_ACR_LATENCY_1WS (0x00000001UL)
7549 #define FLASH_ACR_LATENCY_2WS (0x00000002UL)
7550 #define FLASH_ACR_LATENCY_3WS (0x00000003UL)
7551 #define FLASH_ACR_LATENCY_4WS (0x00000004UL)
7552 #define FLASH_ACR_PRFTEN_Pos (8U)
7553 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
7554 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7555 #define FLASH_ACR_ICEN_Pos (9U)
7556 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
7557 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7558 #define FLASH_ACR_DCEN_Pos (10U)
7559 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
7560 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7561 #define FLASH_ACR_ICRST_Pos (11U)
7562 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
7563 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7564 #define FLASH_ACR_DCRST_Pos (12U)
7565 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
7566 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7567 #define FLASH_ACR_RUN_PD_Pos (13U)
7568 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)
7569 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk
7570 #define FLASH_ACR_SLEEP_PD_Pos (14U)
7571 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)
7572 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk
7574 /******************* Bits definition for FLASH_SR register ******************/
7575 #define FLASH_SR_EOP_Pos (0U)
7576 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
7577 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
7578 #define FLASH_SR_OPERR_Pos (1U)
7579 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
7580 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7581 #define FLASH_SR_PROGERR_Pos (3U)
7582 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)
7583 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
7584 #define FLASH_SR_WRPERR_Pos (4U)
7585 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
7586 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7587 #define FLASH_SR_PGAERR_Pos (5U)
7588 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
7589 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7590 #define FLASH_SR_SIZERR_Pos (6U)
7591 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)
7592 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
7593 #define FLASH_SR_PGSERR_Pos (7U)
7594 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
7595 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7596 #define FLASH_SR_MISERR_Pos (8U)
7597 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)
7598 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
7599 #define FLASH_SR_FASTERR_Pos (9U)
7600 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)
7601 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
7602 #define FLASH_SR_RDERR_Pos (14U)
7603 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
7604 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7605 #define FLASH_SR_OPTVERR_Pos (15U)
7606 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)
7607 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
7608 #define FLASH_SR_BSY_Pos (16U)
7609 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
7610 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
7611 
7612 /******************* Bits definition for FLASH_CR register ******************/
7613 #define FLASH_CR_PG_Pos (0U)
7614 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
7615 #define FLASH_CR_PG FLASH_CR_PG_Msk
7616 #define FLASH_CR_PER_Pos (1U)
7617 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
7618 #define FLASH_CR_PER FLASH_CR_PER_Msk
7619 #define FLASH_CR_MER1_Pos (2U)
7620 #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)
7621 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
7622 #define FLASH_CR_PNB_Pos (3U)
7623 #define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos)
7624 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
7625 #define FLASH_CR_BKER_Pos (11U)
7626 #define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos)
7627 #define FLASH_CR_BKER FLASH_CR_BKER_Msk
7628 #define FLASH_CR_MER2_Pos (15U)
7629 #define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
7630 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7631 #define FLASH_CR_STRT_Pos (16U)
7632 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
7633 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
7634 #define FLASH_CR_OPTSTRT_Pos (17U)
7635 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)
7636 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
7637 #define FLASH_CR_FSTPG_Pos (18U)
7638 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)
7639 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
7640 #define FLASH_CR_EOPIE_Pos (24U)
7641 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
7642 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7643 #define FLASH_CR_ERRIE_Pos (25U)
7644 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
7645 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7646 #define FLASH_CR_RDERRIE_Pos (26U)
7647 #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)
7648 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
7649 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
7650 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)
7651 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
7652 #define FLASH_CR_OPTLOCK_Pos (30U)
7653 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)
7654 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
7655 #define FLASH_CR_LOCK_Pos (31U)
7656 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
7657 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7658 
7659 /******************* Bits definition for FLASH_ECCR register ***************/
7660 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
7661 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)
7662 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
7663 #define FLASH_ECCR_BK_ECC_Pos (19U)
7664 #define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos)
7665 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
7666 #define FLASH_ECCR_SYSF_ECC_Pos (20U)
7667 #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)
7668 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
7669 #define FLASH_ECCR_ECCIE_Pos (24U)
7670 #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos)
7671 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
7672 #define FLASH_ECCR_ECCC_Pos (30U)
7673 #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)
7674 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
7675 #define FLASH_ECCR_ECCD_Pos (31U)
7676 #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)
7677 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
7678 
7679 /******************* Bits definition for FLASH_OPTR register ***************/
7680 #define FLASH_OPTR_RDP_Pos (0U)
7681 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)
7682 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
7683 #define FLASH_OPTR_BOR_LEV_Pos (8U)
7684 #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos)
7685 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
7686 #define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos)
7687 #define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos)
7688 #define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos)
7689 #define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos)
7690 #define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos)
7691 #define FLASH_OPTR_nRST_STOP_Pos (12U)
7692 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)
7693 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
7694 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
7695 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)
7696 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
7697 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
7698 #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)
7699 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
7700 #define FLASH_OPTR_IWDG_SW_Pos (16U)
7701 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)
7702 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
7703 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
7704 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)
7705 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
7706 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
7707 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)
7708 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
7709 #define FLASH_OPTR_WWDG_SW_Pos (19U)
7710 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)
7711 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
7712 #define FLASH_OPTR_BFB2_Pos (20U)
7713 #define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos)
7714 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
7715 #define FLASH_OPTR_DUALBANK_Pos (21U)
7716 #define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos)
7717 #define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk
7718 #define FLASH_OPTR_nBOOT1_Pos (23U)
7719 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)
7720 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
7721 #define FLASH_OPTR_SRAM2_PE_Pos (24U)
7722 #define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)
7723 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
7724 #define FLASH_OPTR_SRAM2_RST_Pos (25U)
7725 #define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)
7726 #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
7727 
7728 /****************** Bits definition for FLASH_PCROP1SR register **********/
7729 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
7730 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)
7731 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
7732 
7733 /****************** Bits definition for FLASH_PCROP1ER register ***********/
7734 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
7735 #define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)
7736 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
7737 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
7738 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)
7739 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
7740 
7741 /****************** Bits definition for FLASH_WRP1AR register ***************/
7742 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
7743 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos)
7744 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
7745 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7746 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos)
7747 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
7748 
7749 /****************** Bits definition for FLASH_WRPB1R register ***************/
7750 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
7751 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos)
7752 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
7753 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7754 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos)
7755 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
7756 
7757 /****************** Bits definition for FLASH_PCROP2SR register **********/
7758 #define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
7759 #define FLASH_PCROP2SR_PCROP2_STRT_Msk (0xFFFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)
7760 #define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
7761 
7762 /****************** Bits definition for FLASH_PCROP2ER register ***********/
7763 #define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
7764 #define FLASH_PCROP2ER_PCROP2_END_Msk (0xFFFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)
7765 #define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
7766 
7767 /****************** Bits definition for FLASH_WRP2AR register ***************/
7768 #define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
7769 #define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_STRT_Pos)
7770 #define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
7771 #define FLASH_WRP2AR_WRP2A_END_Pos (16U)
7772 #define FLASH_WRP2AR_WRP2A_END_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_END_Pos)
7773 #define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
7774 
7775 /****************** Bits definition for FLASH_WRP2BR register ***************/
7776 #define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
7777 #define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_STRT_Pos)
7778 #define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
7779 #define FLASH_WRP2BR_WRP2B_END_Pos (16U)
7780 #define FLASH_WRP2BR_WRP2B_END_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_END_Pos)
7781 #define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
7782 
7783 
7784 /******************************************************************************/
7785 /* */
7786 /* Flexible Memory Controller */
7787 /* */
7788 /******************************************************************************/
7789 /****************** Bit definition for FMC_BCR1 register *******************/
7790 #define FMC_BCR1_CCLKEN_Pos (20U)
7791 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
7792 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
7794 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
7795 #define FMC_BCRx_MBKEN_Pos (0U)
7796 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
7797 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
7798 #define FMC_BCRx_MUXEN_Pos (1U)
7799 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
7800 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
7802 #define FMC_BCRx_MTYP_Pos (2U)
7803 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
7804 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
7805 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
7806 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
7808 #define FMC_BCRx_MWID_Pos (4U)
7809 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
7810 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
7811 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
7812 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
7814 #define FMC_BCRx_FACCEN_Pos (6U)
7815 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
7816 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
7817 #define FMC_BCRx_BURSTEN_Pos (8U)
7818 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
7819 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
7820 #define FMC_BCRx_WAITPOL_Pos (9U)
7821 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
7822 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
7823 #define FMC_BCRx_WAITCFG_Pos (11U)
7824 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
7825 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
7826 #define FMC_BCRx_WREN_Pos (12U)
7827 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
7828 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
7829 #define FMC_BCRx_WAITEN_Pos (13U)
7830 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
7831 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
7832 #define FMC_BCRx_EXTMOD_Pos (14U)
7833 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
7834 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
7835 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
7836 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
7837 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
7839 #define FMC_BCRx_CPSIZE_Pos (16U)
7840 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
7841 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
7842 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
7843 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
7844 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
7846 #define FMC_BCRx_CBURSTRW_Pos (19U)
7847 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
7848 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
7850 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
7851 #define FMC_BTRx_ADDSET_Pos (0U)
7852 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
7853 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
7854 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
7855 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
7856 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
7857 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
7859 #define FMC_BTRx_ADDHLD_Pos (4U)
7860 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
7861 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
7862 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
7863 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
7864 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
7865 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
7867 #define FMC_BTRx_DATAST_Pos (8U)
7868 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
7869 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
7870 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
7871 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
7872 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
7873 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
7874 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
7875 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
7876 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
7877 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
7879 #define FMC_BTRx_BUSTURN_Pos (16U)
7880 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
7881 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
7882 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
7883 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
7884 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
7885 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
7887 #define FMC_BTRx_CLKDIV_Pos (20U)
7888 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
7889 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
7890 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
7891 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
7892 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
7893 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
7895 #define FMC_BTRx_DATLAT_Pos (24U)
7896 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
7897 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
7898 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
7899 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
7900 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
7901 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
7903 #define FMC_BTRx_ACCMOD_Pos (28U)
7904 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
7905 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
7906 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
7907 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
7909 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
7910 #define FMC_BWTRx_ADDSET_Pos (0U)
7911 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
7912 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
7913 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
7914 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
7915 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
7916 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
7918 #define FMC_BWTRx_ADDHLD_Pos (4U)
7919 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
7920 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
7921 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
7922 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
7923 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
7924 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
7926 #define FMC_BWTRx_DATAST_Pos (8U)
7927 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
7928 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
7929 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
7930 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
7931 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
7932 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
7933 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
7934 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
7935 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
7936 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
7938 #define FMC_BWTRx_BUSTURN_Pos (16U)
7939 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
7940 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
7941 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
7942 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
7943 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
7944 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
7946 #define FMC_BWTRx_ACCMOD_Pos (28U)
7947 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
7948 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
7949 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
7950 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
7952 /****************** Bit definition for FMC_PCR register ********************/
7953 #define FMC_PCR_PWAITEN_Pos (1U)
7954 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
7955 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
7956 #define FMC_PCR_PBKEN_Pos (2U)
7957 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
7958 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
7959 #define FMC_PCR_PTYP_Pos (3U)
7960 #define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
7961 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
7963 #define FMC_PCR_PWID_Pos (4U)
7964 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
7965 #define FMC_PCR_PWID FMC_PCR_PWID_Msk
7966 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
7967 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
7969 #define FMC_PCR_ECCEN_Pos (6U)
7970 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
7971 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
7973 #define FMC_PCR_TCLR_Pos (9U)
7974 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
7975 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
7976 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
7977 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
7978 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
7979 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
7981 #define FMC_PCR_TAR_Pos (13U)
7982 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
7983 #define FMC_PCR_TAR FMC_PCR_TAR_Msk
7984 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
7985 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
7986 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
7987 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
7989 #define FMC_PCR_ECCPS_Pos (17U)
7990 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
7991 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
7992 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
7993 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
7994 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
7996 /******************* Bit definition for FMC_SR register ********************/
7997 #define FMC_SR_IRS_Pos (0U)
7998 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
7999 #define FMC_SR_IRS FMC_SR_IRS_Msk
8000 #define FMC_SR_ILS_Pos (1U)
8001 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
8002 #define FMC_SR_ILS FMC_SR_ILS_Msk
8003 #define FMC_SR_IFS_Pos (2U)
8004 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
8005 #define FMC_SR_IFS FMC_SR_IFS_Msk
8006 #define FMC_SR_IREN_Pos (3U)
8007 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
8008 #define FMC_SR_IREN FMC_SR_IREN_Msk
8009 #define FMC_SR_ILEN_Pos (4U)
8010 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
8011 #define FMC_SR_ILEN FMC_SR_ILEN_Msk
8012 #define FMC_SR_IFEN_Pos (5U)
8013 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
8014 #define FMC_SR_IFEN FMC_SR_IFEN_Msk
8015 #define FMC_SR_FEMPT_Pos (6U)
8016 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
8017 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
8019 /****************** Bit definition for FMC_PMEM register ******************/
8020 #define FMC_PMEM_MEMSET_Pos (0U)
8021 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
8022 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
8023 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
8024 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
8025 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
8026 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
8027 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
8028 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
8029 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
8030 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
8032 #define FMC_PMEM_MEMWAIT_Pos (8U)
8033 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
8034 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
8035 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
8036 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
8037 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
8038 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
8039 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
8040 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
8041 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
8042 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
8044 #define FMC_PMEM_MEMHOLD_Pos (16U)
8045 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
8046 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
8047 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
8048 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
8049 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
8050 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
8051 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
8052 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
8053 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
8054 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
8056 #define FMC_PMEM_MEMHIZ_Pos (24U)
8057 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
8058 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
8059 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
8060 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
8061 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
8062 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
8063 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
8064 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
8065 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
8066 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
8068 /****************** Bit definition for FMC_PATT register *******************/
8069 #define FMC_PATT_ATTSET_Pos (0U)
8070 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
8071 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
8072 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
8073 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
8074 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
8075 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
8076 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
8077 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
8078 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
8079 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
8081 #define FMC_PATT_ATTWAIT_Pos (8U)
8082 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
8083 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
8084 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
8085 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
8086 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
8087 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
8088 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
8089 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
8090 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
8091 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
8093 #define FMC_PATT_ATTHOLD_Pos (16U)
8094 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
8095 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
8096 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
8097 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
8098 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
8099 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
8100 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
8101 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
8102 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
8103 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
8105 #define FMC_PATT_ATTHIZ_Pos (24U)
8106 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
8107 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
8108 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
8109 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
8110 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
8111 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
8112 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
8113 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
8114 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
8115 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
8117 /****************** Bit definition for FMC_ECCR register *******************/
8118 #define FMC_ECCR_ECC_Pos (0U)
8119 #define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)
8120 #define FMC_ECCR_ECC FMC_ECCR_ECC_Msk
8122 /******************************************************************************/
8123 /* */
8124 /* General Purpose IOs (GPIO) */
8125 /* */
8126 /******************************************************************************/
8127 /****************** Bits definition for GPIO_MODER register *****************/
8128 #define GPIO_MODER_MODE0_Pos (0U)
8129 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
8130 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
8131 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
8132 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
8133 #define GPIO_MODER_MODE1_Pos (2U)
8134 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
8135 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
8136 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
8137 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
8138 #define GPIO_MODER_MODE2_Pos (4U)
8139 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
8140 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
8141 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
8142 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
8143 #define GPIO_MODER_MODE3_Pos (6U)
8144 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
8145 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
8146 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
8147 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
8148 #define GPIO_MODER_MODE4_Pos (8U)
8149 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
8150 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
8151 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
8152 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
8153 #define GPIO_MODER_MODE5_Pos (10U)
8154 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
8155 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
8156 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
8157 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
8158 #define GPIO_MODER_MODE6_Pos (12U)
8159 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
8160 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
8161 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
8162 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
8163 #define GPIO_MODER_MODE7_Pos (14U)
8164 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
8165 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
8166 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
8167 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
8168 #define GPIO_MODER_MODE8_Pos (16U)
8169 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
8170 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
8171 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
8172 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
8173 #define GPIO_MODER_MODE9_Pos (18U)
8174 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
8175 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
8176 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
8177 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
8178 #define GPIO_MODER_MODE10_Pos (20U)
8179 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
8180 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8181 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
8182 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
8183 #define GPIO_MODER_MODE11_Pos (22U)
8184 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
8185 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8186 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
8187 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
8188 #define GPIO_MODER_MODE12_Pos (24U)
8189 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
8190 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8191 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
8192 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
8193 #define GPIO_MODER_MODE13_Pos (26U)
8194 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
8195 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8196 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
8197 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
8198 #define GPIO_MODER_MODE14_Pos (28U)
8199 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
8200 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8201 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
8202 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
8203 #define GPIO_MODER_MODE15_Pos (30U)
8204 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
8205 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8206 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
8207 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
8209 /* Legacy defines */
8210 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
8211 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
8212 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
8213 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
8214 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
8215 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
8216 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
8217 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
8218 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
8219 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
8220 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
8221 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
8222 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
8223 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
8224 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
8225 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
8226 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
8227 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
8228 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
8229 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
8230 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
8231 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
8232 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
8233 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
8234 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
8235 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
8236 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
8237 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
8238 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
8239 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
8240 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
8241 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
8242 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
8243 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
8244 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
8245 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
8246 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
8247 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
8248 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
8249 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
8250 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
8251 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
8252 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
8253 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
8254 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
8255 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
8256 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
8257 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
8258 
8259 /****************** Bits definition for GPIO_OTYPER register ****************/
8260 #define GPIO_OTYPER_OT0_Pos (0U)
8261 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
8262 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8263 #define GPIO_OTYPER_OT1_Pos (1U)
8264 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
8265 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8266 #define GPIO_OTYPER_OT2_Pos (2U)
8267 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
8268 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8269 #define GPIO_OTYPER_OT3_Pos (3U)
8270 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
8271 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8272 #define GPIO_OTYPER_OT4_Pos (4U)
8273 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
8274 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8275 #define GPIO_OTYPER_OT5_Pos (5U)
8276 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
8277 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8278 #define GPIO_OTYPER_OT6_Pos (6U)
8279 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
8280 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8281 #define GPIO_OTYPER_OT7_Pos (7U)
8282 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
8283 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8284 #define GPIO_OTYPER_OT8_Pos (8U)
8285 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
8286 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8287 #define GPIO_OTYPER_OT9_Pos (9U)
8288 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
8289 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8290 #define GPIO_OTYPER_OT10_Pos (10U)
8291 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
8292 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8293 #define GPIO_OTYPER_OT11_Pos (11U)
8294 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
8295 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8296 #define GPIO_OTYPER_OT12_Pos (12U)
8297 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
8298 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8299 #define GPIO_OTYPER_OT13_Pos (13U)
8300 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
8301 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8302 #define GPIO_OTYPER_OT14_Pos (14U)
8303 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
8304 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8305 #define GPIO_OTYPER_OT15_Pos (15U)
8306 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
8307 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8308 
8309 /* Legacy defines */
8310 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8311 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8312 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8313 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8314 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8315 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8316 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8317 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8318 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8319 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8320 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8321 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8322 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8323 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8324 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8325 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8326 
8327 /****************** Bits definition for GPIO_OSPEEDR register ***************/
8328 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8329 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
8330 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8331 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
8332 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
8333 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8334 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
8335 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8336 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
8337 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
8338 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8339 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
8340 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8341 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
8342 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
8343 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8344 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
8345 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8346 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
8347 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
8348 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8349 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
8350 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8351 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
8352 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
8353 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8354 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
8355 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8356 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
8357 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
8358 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8359 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
8360 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8361 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
8362 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
8363 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8364 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
8365 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8366 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
8367 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
8368 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8369 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
8370 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8371 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
8372 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
8373 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8374 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
8375 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8376 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
8377 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
8378 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8379 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
8380 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8381 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
8382 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
8383 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8384 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
8385 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8386 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
8387 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
8388 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8389 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
8390 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8391 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
8392 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
8393 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8394 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
8395 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8396 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
8397 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
8398 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8399 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
8400 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8401 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
8402 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
8403 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8404 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
8405 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8406 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
8407 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
8409 /* Legacy defines */
8410 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8411 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8412 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8413 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8414 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8415 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8416 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8417 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8418 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8419 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8420 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8421 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8422 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8423 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8424 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8425 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8426 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8427 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8428 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8429 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8430 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8431 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8432 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8433 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8434 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8435 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8436 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8437 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8438 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8439 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8440 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8441 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8442 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8443 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8444 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8445 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8446 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8447 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8448 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8449 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8450 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8451 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8452 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8453 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8454 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8455 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8456 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8457 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8458 
8459 /****************** Bits definition for GPIO_PUPDR register *****************/
8460 #define GPIO_PUPDR_PUPD0_Pos (0U)
8461 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
8462 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8463 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
8464 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
8465 #define GPIO_PUPDR_PUPD1_Pos (2U)
8466 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
8467 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8468 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
8469 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
8470 #define GPIO_PUPDR_PUPD2_Pos (4U)
8471 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
8472 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8473 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
8474 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
8475 #define GPIO_PUPDR_PUPD3_Pos (6U)
8476 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
8477 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8478 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
8479 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
8480 #define GPIO_PUPDR_PUPD4_Pos (8U)
8481 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
8482 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8483 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
8484 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
8485 #define GPIO_PUPDR_PUPD5_Pos (10U)
8486 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
8487 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8488 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
8489 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
8490 #define GPIO_PUPDR_PUPD6_Pos (12U)
8491 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
8492 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8493 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
8494 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
8495 #define GPIO_PUPDR_PUPD7_Pos (14U)
8496 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
8497 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8498 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
8499 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
8500 #define GPIO_PUPDR_PUPD8_Pos (16U)
8501 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
8502 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8503 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
8504 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
8505 #define GPIO_PUPDR_PUPD9_Pos (18U)
8506 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
8507 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8508 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
8509 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
8510 #define GPIO_PUPDR_PUPD10_Pos (20U)
8511 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
8512 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8513 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
8514 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
8515 #define GPIO_PUPDR_PUPD11_Pos (22U)
8516 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
8517 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8518 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
8519 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
8520 #define GPIO_PUPDR_PUPD12_Pos (24U)
8521 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
8522 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8523 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
8524 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
8525 #define GPIO_PUPDR_PUPD13_Pos (26U)
8526 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
8527 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8528 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
8529 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
8530 #define GPIO_PUPDR_PUPD14_Pos (28U)
8531 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
8532 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8533 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
8534 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
8535 #define GPIO_PUPDR_PUPD15_Pos (30U)
8536 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
8537 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8538 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
8539 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
8541 /* Legacy defines */
8542 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8543 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8544 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8545 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8546 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8547 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8548 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8549 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8550 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8551 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8552 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8553 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8554 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8555 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8556 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8557 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8558 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8559 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8560 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8561 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8562 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8563 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8564 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8565 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8566 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8567 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8568 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8569 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8570 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8571 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8572 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8573 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8574 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8575 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8576 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8577 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8578 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8579 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8580 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8581 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8582 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8583 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8584 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8585 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8586 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8587 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8588 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8589 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8590 
8591 /****************** Bits definition for GPIO_IDR register *******************/
8592 #define GPIO_IDR_ID0_Pos (0U)
8593 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8594 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8595 #define GPIO_IDR_ID1_Pos (1U)
8596 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8597 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8598 #define GPIO_IDR_ID2_Pos (2U)
8599 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8600 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8601 #define GPIO_IDR_ID3_Pos (3U)
8602 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8603 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8604 #define GPIO_IDR_ID4_Pos (4U)
8605 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8606 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8607 #define GPIO_IDR_ID5_Pos (5U)
8608 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8609 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8610 #define GPIO_IDR_ID6_Pos (6U)
8611 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8612 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8613 #define GPIO_IDR_ID7_Pos (7U)
8614 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8615 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8616 #define GPIO_IDR_ID8_Pos (8U)
8617 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8618 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8619 #define GPIO_IDR_ID9_Pos (9U)
8620 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8621 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8622 #define GPIO_IDR_ID10_Pos (10U)
8623 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8624 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8625 #define GPIO_IDR_ID11_Pos (11U)
8626 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8627 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8628 #define GPIO_IDR_ID12_Pos (12U)
8629 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8630 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8631 #define GPIO_IDR_ID13_Pos (13U)
8632 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8633 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8634 #define GPIO_IDR_ID14_Pos (14U)
8635 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8636 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8637 #define GPIO_IDR_ID15_Pos (15U)
8638 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8639 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8640 
8641 /* Legacy defines */
8642 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8643 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8644 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8645 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8646 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8647 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8648 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8649 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8650 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8651 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8652 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8653 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8654 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8655 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8656 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8657 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8658 
8659 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
8660 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
8661 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
8662 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
8663 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
8664 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
8665 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
8666 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
8667 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
8668 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
8669 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
8670 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
8671 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
8672 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
8673 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
8674 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
8675 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
8676 
8677 /****************** Bits definition for GPIO_ODR register *******************/
8678 #define GPIO_ODR_OD0_Pos (0U)
8679 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8680 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8681 #define GPIO_ODR_OD1_Pos (1U)
8682 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8683 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8684 #define GPIO_ODR_OD2_Pos (2U)
8685 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8686 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8687 #define GPIO_ODR_OD3_Pos (3U)
8688 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8689 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8690 #define GPIO_ODR_OD4_Pos (4U)
8691 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8692 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8693 #define GPIO_ODR_OD5_Pos (5U)
8694 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8695 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8696 #define GPIO_ODR_OD6_Pos (6U)
8697 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8698 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8699 #define GPIO_ODR_OD7_Pos (7U)
8700 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8701 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8702 #define GPIO_ODR_OD8_Pos (8U)
8703 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8704 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8705 #define GPIO_ODR_OD9_Pos (9U)
8706 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8707 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8708 #define GPIO_ODR_OD10_Pos (10U)
8709 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8710 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8711 #define GPIO_ODR_OD11_Pos (11U)
8712 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8713 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8714 #define GPIO_ODR_OD12_Pos (12U)
8715 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8716 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8717 #define GPIO_ODR_OD13_Pos (13U)
8718 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8719 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8720 #define GPIO_ODR_OD14_Pos (14U)
8721 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8722 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8723 #define GPIO_ODR_OD15_Pos (15U)
8724 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8725 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8726 
8727 /* Legacy defines */
8728 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8729 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8730 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8731 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8732 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8733 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8734 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8735 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8736 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8737 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8738 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8739 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8740 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8741 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8742 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8743 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8744 
8745 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
8746 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
8747 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
8748 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
8749 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
8750 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
8751 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
8752 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
8753 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
8754 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
8755 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
8756 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
8757 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
8758 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
8759 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
8760 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
8761 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
8762 
8763 /****************** Bits definition for GPIO_BSRR register ******************/
8764 #define GPIO_BSRR_BS0_Pos (0U)
8765 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8766 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8767 #define GPIO_BSRR_BS1_Pos (1U)
8768 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8769 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8770 #define GPIO_BSRR_BS2_Pos (2U)
8771 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8772 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8773 #define GPIO_BSRR_BS3_Pos (3U)
8774 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8775 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8776 #define GPIO_BSRR_BS4_Pos (4U)
8777 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8778 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8779 #define GPIO_BSRR_BS5_Pos (5U)
8780 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8781 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8782 #define GPIO_BSRR_BS6_Pos (6U)
8783 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8784 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8785 #define GPIO_BSRR_BS7_Pos (7U)
8786 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8787 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8788 #define GPIO_BSRR_BS8_Pos (8U)
8789 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8790 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8791 #define GPIO_BSRR_BS9_Pos (9U)
8792 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8793 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8794 #define GPIO_BSRR_BS10_Pos (10U)
8795 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8796 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8797 #define GPIO_BSRR_BS11_Pos (11U)
8798 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8799 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8800 #define GPIO_BSRR_BS12_Pos (12U)
8801 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8802 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8803 #define GPIO_BSRR_BS13_Pos (13U)
8804 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8805 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8806 #define GPIO_BSRR_BS14_Pos (14U)
8807 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8808 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8809 #define GPIO_BSRR_BS15_Pos (15U)
8810 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8811 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8812 #define GPIO_BSRR_BR0_Pos (16U)
8813 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8814 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8815 #define GPIO_BSRR_BR1_Pos (17U)
8816 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8817 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8818 #define GPIO_BSRR_BR2_Pos (18U)
8819 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8820 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8821 #define GPIO_BSRR_BR3_Pos (19U)
8822 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8823 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8824 #define GPIO_BSRR_BR4_Pos (20U)
8825 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8826 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8827 #define GPIO_BSRR_BR5_Pos (21U)
8828 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8829 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8830 #define GPIO_BSRR_BR6_Pos (22U)
8831 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8832 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8833 #define GPIO_BSRR_BR7_Pos (23U)
8834 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8835 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8836 #define GPIO_BSRR_BR8_Pos (24U)
8837 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8838 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8839 #define GPIO_BSRR_BR9_Pos (25U)
8840 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8841 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8842 #define GPIO_BSRR_BR10_Pos (26U)
8843 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8844 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8845 #define GPIO_BSRR_BR11_Pos (27U)
8846 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8847 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8848 #define GPIO_BSRR_BR12_Pos (28U)
8849 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8850 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8851 #define GPIO_BSRR_BR13_Pos (29U)
8852 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8853 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8854 #define GPIO_BSRR_BR14_Pos (30U)
8855 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8856 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8857 #define GPIO_BSRR_BR15_Pos (31U)
8858 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8859 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8860 
8861 /* Legacy defines */
8862 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8863 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8864 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8865 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8866 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8867 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8868 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8869 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8870 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8871 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8872 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8873 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8874 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8875 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8876 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8877 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8878 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8879 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8880 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8881 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8882 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8883 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8884 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8885 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8886 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8887 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8888 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8889 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8890 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8891 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8892 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8893 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8894 
8895 /****************** Bit definition for GPIO_LCKR register *********************/
8896 #define GPIO_LCKR_LCK0_Pos (0U)
8897 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8898 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8899 #define GPIO_LCKR_LCK1_Pos (1U)
8900 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8901 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8902 #define GPIO_LCKR_LCK2_Pos (2U)
8903 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8904 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8905 #define GPIO_LCKR_LCK3_Pos (3U)
8906 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8907 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8908 #define GPIO_LCKR_LCK4_Pos (4U)
8909 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8910 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8911 #define GPIO_LCKR_LCK5_Pos (5U)
8912 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8913 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8914 #define GPIO_LCKR_LCK6_Pos (6U)
8915 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8916 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8917 #define GPIO_LCKR_LCK7_Pos (7U)
8918 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8919 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8920 #define GPIO_LCKR_LCK8_Pos (8U)
8921 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8922 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8923 #define GPIO_LCKR_LCK9_Pos (9U)
8924 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8925 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8926 #define GPIO_LCKR_LCK10_Pos (10U)
8927 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8928 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8929 #define GPIO_LCKR_LCK11_Pos (11U)
8930 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8931 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8932 #define GPIO_LCKR_LCK12_Pos (12U)
8933 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8934 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8935 #define GPIO_LCKR_LCK13_Pos (13U)
8936 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8937 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8938 #define GPIO_LCKR_LCK14_Pos (14U)
8939 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8940 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8941 #define GPIO_LCKR_LCK15_Pos (15U)
8942 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8943 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8944 #define GPIO_LCKR_LCKK_Pos (16U)
8945 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8946 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8947 
8948 /****************** Bit definition for GPIO_AFRL register *********************/
8949 #define GPIO_AFRL_AFSEL0_Pos (0U)
8950 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8951 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8952 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8953 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8954 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8955 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8956 #define GPIO_AFRL_AFSEL1_Pos (4U)
8957 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8958 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8959 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8960 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8961 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8962 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8963 #define GPIO_AFRL_AFSEL2_Pos (8U)
8964 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8965 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8966 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8967 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8968 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8969 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8970 #define GPIO_AFRL_AFSEL3_Pos (12U)
8971 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8972 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8973 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8974 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8975 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8976 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8977 #define GPIO_AFRL_AFSEL4_Pos (16U)
8978 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8979 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8980 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8981 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8982 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8983 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8984 #define GPIO_AFRL_AFSEL5_Pos (20U)
8985 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8986 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8987 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8988 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8989 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8990 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8991 #define GPIO_AFRL_AFSEL6_Pos (24U)
8992 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8993 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8994 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
8995 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
8996 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
8997 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
8998 #define GPIO_AFRL_AFSEL7_Pos (28U)
8999 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
9000 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
9001 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
9002 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
9003 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
9004 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
9006 /* Legacy defines */
9007 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
9008 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
9009 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
9010 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
9011 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
9012 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
9013 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9014 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9015 
9016 /****************** Bit definition for GPIO_AFRH register *********************/
9017 #define GPIO_AFRH_AFSEL8_Pos (0U)
9018 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
9019 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9020 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
9021 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
9022 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
9023 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
9024 #define GPIO_AFRH_AFSEL9_Pos (4U)
9025 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
9026 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9027 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
9028 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
9029 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
9030 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
9031 #define GPIO_AFRH_AFSEL10_Pos (8U)
9032 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
9033 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9034 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
9035 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
9036 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
9037 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
9038 #define GPIO_AFRH_AFSEL11_Pos (12U)
9039 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
9040 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9041 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
9042 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
9043 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
9044 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
9045 #define GPIO_AFRH_AFSEL12_Pos (16U)
9046 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
9047 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9048 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
9049 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
9050 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
9051 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
9052 #define GPIO_AFRH_AFSEL13_Pos (20U)
9053 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
9054 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9055 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
9056 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
9057 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
9058 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
9059 #define GPIO_AFRH_AFSEL14_Pos (24U)
9060 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
9061 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9062 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
9063 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
9064 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
9065 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
9066 #define GPIO_AFRH_AFSEL15_Pos (28U)
9067 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
9068 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9069 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
9070 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
9071 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
9072 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
9074 /* Legacy defines */
9075 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9076 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9077 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9078 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9079 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9080 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9081 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9082 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9083 
9084 /****************** Bits definition for GPIO_BRR register ******************/
9085 #define GPIO_BRR_BR0_Pos (0U)
9086 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)
9087 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
9088 #define GPIO_BRR_BR1_Pos (1U)
9089 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)
9090 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
9091 #define GPIO_BRR_BR2_Pos (2U)
9092 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)
9093 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
9094 #define GPIO_BRR_BR3_Pos (3U)
9095 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)
9096 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
9097 #define GPIO_BRR_BR4_Pos (4U)
9098 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)
9099 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
9100 #define GPIO_BRR_BR5_Pos (5U)
9101 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)
9102 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
9103 #define GPIO_BRR_BR6_Pos (6U)
9104 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)
9105 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
9106 #define GPIO_BRR_BR7_Pos (7U)
9107 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)
9108 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
9109 #define GPIO_BRR_BR8_Pos (8U)
9110 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)
9111 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
9112 #define GPIO_BRR_BR9_Pos (9U)
9113 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)
9114 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
9115 #define GPIO_BRR_BR10_Pos (10U)
9116 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)
9117 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
9118 #define GPIO_BRR_BR11_Pos (11U)
9119 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)
9120 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
9121 #define GPIO_BRR_BR12_Pos (12U)
9122 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)
9123 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
9124 #define GPIO_BRR_BR13_Pos (13U)
9125 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)
9126 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
9127 #define GPIO_BRR_BR14_Pos (14U)
9128 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)
9129 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
9130 #define GPIO_BRR_BR15_Pos (15U)
9131 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)
9132 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
9133 
9134 /* Legacy defines */
9135 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
9136 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
9137 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
9138 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
9139 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
9140 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
9141 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
9142 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
9143 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
9144 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
9145 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
9146 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
9147 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
9148 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
9149 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
9150 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
9151 
9152 
9153 /****************** Bits definition for GPIO_ASCR register *******************/
9154 #define GPIO_ASCR_ASC0_Pos (0U)
9155 #define GPIO_ASCR_ASC0_Msk (0x1UL << GPIO_ASCR_ASC0_Pos)
9156 #define GPIO_ASCR_ASC0 GPIO_ASCR_ASC0_Msk
9157 #define GPIO_ASCR_ASC1_Pos (1U)
9158 #define GPIO_ASCR_ASC1_Msk (0x1UL << GPIO_ASCR_ASC1_Pos)
9159 #define GPIO_ASCR_ASC1 GPIO_ASCR_ASC1_Msk
9160 #define GPIO_ASCR_ASC2_Pos (2U)
9161 #define GPIO_ASCR_ASC2_Msk (0x1UL << GPIO_ASCR_ASC2_Pos)
9162 #define GPIO_ASCR_ASC2 GPIO_ASCR_ASC2_Msk
9163 #define GPIO_ASCR_ASC3_Pos (3U)
9164 #define GPIO_ASCR_ASC3_Msk (0x1UL << GPIO_ASCR_ASC3_Pos)
9165 #define GPIO_ASCR_ASC3 GPIO_ASCR_ASC3_Msk
9166 #define GPIO_ASCR_ASC4_Pos (4U)
9167 #define GPIO_ASCR_ASC4_Msk (0x1UL << GPIO_ASCR_ASC4_Pos)
9168 #define GPIO_ASCR_ASC4 GPIO_ASCR_ASC4_Msk
9169 #define GPIO_ASCR_ASC5_Pos (5U)
9170 #define GPIO_ASCR_ASC5_Msk (0x1UL << GPIO_ASCR_ASC5_Pos)
9171 #define GPIO_ASCR_ASC5 GPIO_ASCR_ASC5_Msk
9172 #define GPIO_ASCR_ASC6_Pos (6U)
9173 #define GPIO_ASCR_ASC6_Msk (0x1UL << GPIO_ASCR_ASC6_Pos)
9174 #define GPIO_ASCR_ASC6 GPIO_ASCR_ASC6_Msk
9175 #define GPIO_ASCR_ASC7_Pos (7U)
9176 #define GPIO_ASCR_ASC7_Msk (0x1UL << GPIO_ASCR_ASC7_Pos)
9177 #define GPIO_ASCR_ASC7 GPIO_ASCR_ASC7_Msk
9178 #define GPIO_ASCR_ASC8_Pos (8U)
9179 #define GPIO_ASCR_ASC8_Msk (0x1UL << GPIO_ASCR_ASC8_Pos)
9180 #define GPIO_ASCR_ASC8 GPIO_ASCR_ASC8_Msk
9181 #define GPIO_ASCR_ASC9_Pos (9U)
9182 #define GPIO_ASCR_ASC9_Msk (0x1UL << GPIO_ASCR_ASC9_Pos)
9183 #define GPIO_ASCR_ASC9 GPIO_ASCR_ASC9_Msk
9184 #define GPIO_ASCR_ASC10_Pos (10U)
9185 #define GPIO_ASCR_ASC10_Msk (0x1UL << GPIO_ASCR_ASC10_Pos)
9186 #define GPIO_ASCR_ASC10 GPIO_ASCR_ASC10_Msk
9187 #define GPIO_ASCR_ASC11_Pos (11U)
9188 #define GPIO_ASCR_ASC11_Msk (0x1UL << GPIO_ASCR_ASC11_Pos)
9189 #define GPIO_ASCR_ASC11 GPIO_ASCR_ASC11_Msk
9190 #define GPIO_ASCR_ASC12_Pos (12U)
9191 #define GPIO_ASCR_ASC12_Msk (0x1UL << GPIO_ASCR_ASC12_Pos)
9192 #define GPIO_ASCR_ASC12 GPIO_ASCR_ASC12_Msk
9193 #define GPIO_ASCR_ASC13_Pos (13U)
9194 #define GPIO_ASCR_ASC13_Msk (0x1UL << GPIO_ASCR_ASC13_Pos)
9195 #define GPIO_ASCR_ASC13 GPIO_ASCR_ASC13_Msk
9196 #define GPIO_ASCR_ASC14_Pos (14U)
9197 #define GPIO_ASCR_ASC14_Msk (0x1UL << GPIO_ASCR_ASC14_Pos)
9198 #define GPIO_ASCR_ASC14 GPIO_ASCR_ASC14_Msk
9199 #define GPIO_ASCR_ASC15_Pos (15U)
9200 #define GPIO_ASCR_ASC15_Msk (0x1UL << GPIO_ASCR_ASC15_Pos)
9201 #define GPIO_ASCR_ASC15 GPIO_ASCR_ASC15_Msk
9202 
9203 /* Legacy defines */
9204 #define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
9205 #define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
9206 #define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
9207 #define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
9208 #define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
9209 #define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
9210 #define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
9211 #define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
9212 #define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
9213 #define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
9214 #define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
9215 #define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
9216 #define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
9217 #define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
9218 #define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
9219 #define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
9220 
9221 /******************************************************************************/
9222 /* */
9223 /* Inter-integrated Circuit Interface (I2C) */
9224 /* */
9225 /******************************************************************************/
9226 /******************* Bit definition for I2C_CR1 register *******************/
9227 #define I2C_CR1_PE_Pos (0U)
9228 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9229 #define I2C_CR1_PE I2C_CR1_PE_Msk
9230 #define I2C_CR1_TXIE_Pos (1U)
9231 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
9232 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
9233 #define I2C_CR1_RXIE_Pos (2U)
9234 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
9235 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
9236 #define I2C_CR1_ADDRIE_Pos (3U)
9237 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
9238 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
9239 #define I2C_CR1_NACKIE_Pos (4U)
9240 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
9241 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
9242 #define I2C_CR1_STOPIE_Pos (5U)
9243 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
9244 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
9245 #define I2C_CR1_TCIE_Pos (6U)
9246 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
9247 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
9248 #define I2C_CR1_ERRIE_Pos (7U)
9249 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
9250 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
9251 #define I2C_CR1_DNF_Pos (8U)
9252 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
9253 #define I2C_CR1_DNF I2C_CR1_DNF_Msk
9254 #define I2C_CR1_ANFOFF_Pos (12U)
9255 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
9256 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
9257 #define I2C_CR1_SWRST_Pos (13U)
9258 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
9259 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
9260 #define I2C_CR1_TXDMAEN_Pos (14U)
9261 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
9262 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
9263 #define I2C_CR1_RXDMAEN_Pos (15U)
9264 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
9265 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
9266 #define I2C_CR1_SBC_Pos (16U)
9267 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
9268 #define I2C_CR1_SBC I2C_CR1_SBC_Msk
9269 #define I2C_CR1_NOSTRETCH_Pos (17U)
9270 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9271 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9272 #define I2C_CR1_WUPEN_Pos (18U)
9273 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
9274 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
9275 #define I2C_CR1_GCEN_Pos (19U)
9276 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
9277 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
9278 #define I2C_CR1_SMBHEN_Pos (20U)
9279 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
9280 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
9281 #define I2C_CR1_SMBDEN_Pos (21U)
9282 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
9283 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
9284 #define I2C_CR1_ALERTEN_Pos (22U)
9285 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
9286 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
9287 #define I2C_CR1_PECEN_Pos (23U)
9288 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
9289 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
9291 /****************** Bit definition for I2C_CR2 register ********************/
9292 #define I2C_CR2_SADD_Pos (0U)
9293 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
9294 #define I2C_CR2_SADD I2C_CR2_SADD_Msk
9295 #define I2C_CR2_RD_WRN_Pos (10U)
9296 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
9297 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
9298 #define I2C_CR2_ADD10_Pos (11U)
9299 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
9300 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
9301 #define I2C_CR2_HEAD10R_Pos (12U)
9302 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
9303 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
9304 #define I2C_CR2_START_Pos (13U)
9305 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
9306 #define I2C_CR2_START I2C_CR2_START_Msk
9307 #define I2C_CR2_STOP_Pos (14U)
9308 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
9309 #define I2C_CR2_STOP I2C_CR2_STOP_Msk
9310 #define I2C_CR2_NACK_Pos (15U)
9311 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
9312 #define I2C_CR2_NACK I2C_CR2_NACK_Msk
9313 #define I2C_CR2_NBYTES_Pos (16U)
9314 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
9315 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
9316 #define I2C_CR2_RELOAD_Pos (24U)
9317 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
9318 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
9319 #define I2C_CR2_AUTOEND_Pos (25U)
9320 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
9321 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
9322 #define I2C_CR2_PECBYTE_Pos (26U)
9323 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
9324 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
9326 /******************* Bit definition for I2C_OAR1 register ******************/
9327 #define I2C_OAR1_OA1_Pos (0U)
9328 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
9329 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
9330 #define I2C_OAR1_OA1MODE_Pos (10U)
9331 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
9332 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
9333 #define I2C_OAR1_OA1EN_Pos (15U)
9334 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
9335 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
9337 /******************* Bit definition for I2C_OAR2 register ******************/
9338 #define I2C_OAR2_OA2_Pos (1U)
9339 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
9340 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
9341 #define I2C_OAR2_OA2MSK_Pos (8U)
9342 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
9343 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
9344 #define I2C_OAR2_OA2NOMASK (0x00000000UL)
9345 #define I2C_OAR2_OA2MASK01_Pos (8U)
9346 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
9347 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
9348 #define I2C_OAR2_OA2MASK02_Pos (9U)
9349 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
9350 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
9351 #define I2C_OAR2_OA2MASK03_Pos (8U)
9352 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
9353 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
9354 #define I2C_OAR2_OA2MASK04_Pos (10U)
9355 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
9356 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
9357 #define I2C_OAR2_OA2MASK05_Pos (8U)
9358 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
9359 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
9360 #define I2C_OAR2_OA2MASK06_Pos (9U)
9361 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
9362 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
9363 #define I2C_OAR2_OA2MASK07_Pos (8U)
9364 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
9365 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
9366 #define I2C_OAR2_OA2EN_Pos (15U)
9367 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
9368 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
9370 /******************* Bit definition for I2C_TIMINGR register *******************/
9371 #define I2C_TIMINGR_SCLL_Pos (0U)
9372 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
9373 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
9374 #define I2C_TIMINGR_SCLH_Pos (8U)
9375 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
9376 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
9377 #define I2C_TIMINGR_SDADEL_Pos (16U)
9378 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
9379 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
9380 #define I2C_TIMINGR_SCLDEL_Pos (20U)
9381 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
9382 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
9383 #define I2C_TIMINGR_PRESC_Pos (28U)
9384 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
9385 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
9387 /******************* Bit definition for I2C_TIMEOUTR register *******************/
9388 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9389 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
9390 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
9391 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
9392 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
9393 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
9394 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9395 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
9396 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
9397 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9398 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
9399 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
9400 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
9401 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
9402 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
9404 /****************** Bit definition for I2C_ISR register *********************/
9405 #define I2C_ISR_TXE_Pos (0U)
9406 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
9407 #define I2C_ISR_TXE I2C_ISR_TXE_Msk
9408 #define I2C_ISR_TXIS_Pos (1U)
9409 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
9410 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
9411 #define I2C_ISR_RXNE_Pos (2U)
9412 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
9413 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
9414 #define I2C_ISR_ADDR_Pos (3U)
9415 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
9416 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
9417 #define I2C_ISR_NACKF_Pos (4U)
9418 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
9419 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
9420 #define I2C_ISR_STOPF_Pos (5U)
9421 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
9422 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
9423 #define I2C_ISR_TC_Pos (6U)
9424 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
9425 #define I2C_ISR_TC I2C_ISR_TC_Msk
9426 #define I2C_ISR_TCR_Pos (7U)
9427 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
9428 #define I2C_ISR_TCR I2C_ISR_TCR_Msk
9429 #define I2C_ISR_BERR_Pos (8U)
9430 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
9431 #define I2C_ISR_BERR I2C_ISR_BERR_Msk
9432 #define I2C_ISR_ARLO_Pos (9U)
9433 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
9434 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
9435 #define I2C_ISR_OVR_Pos (10U)
9436 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
9437 #define I2C_ISR_OVR I2C_ISR_OVR_Msk
9438 #define I2C_ISR_PECERR_Pos (11U)
9439 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
9440 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
9441 #define I2C_ISR_TIMEOUT_Pos (12U)
9442 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
9443 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
9444 #define I2C_ISR_ALERT_Pos (13U)
9445 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
9446 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
9447 #define I2C_ISR_BUSY_Pos (15U)
9448 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
9449 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
9450 #define I2C_ISR_DIR_Pos (16U)
9451 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
9452 #define I2C_ISR_DIR I2C_ISR_DIR_Msk
9453 #define I2C_ISR_ADDCODE_Pos (17U)
9454 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
9455 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
9457 /****************** Bit definition for I2C_ICR register *********************/
9458 #define I2C_ICR_ADDRCF_Pos (3U)
9459 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
9460 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
9461 #define I2C_ICR_NACKCF_Pos (4U)
9462 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
9463 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
9464 #define I2C_ICR_STOPCF_Pos (5U)
9465 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
9466 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
9467 #define I2C_ICR_BERRCF_Pos (8U)
9468 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
9469 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
9470 #define I2C_ICR_ARLOCF_Pos (9U)
9471 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
9472 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
9473 #define I2C_ICR_OVRCF_Pos (10U)
9474 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
9475 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
9476 #define I2C_ICR_PECCF_Pos (11U)
9477 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
9478 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
9479 #define I2C_ICR_TIMOUTCF_Pos (12U)
9480 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
9481 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
9482 #define I2C_ICR_ALERTCF_Pos (13U)
9483 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
9484 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
9486 /****************** Bit definition for I2C_PECR register *********************/
9487 #define I2C_PECR_PEC_Pos (0U)
9488 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
9489 #define I2C_PECR_PEC I2C_PECR_PEC_Msk
9491 /****************** Bit definition for I2C_RXDR register *********************/
9492 #define I2C_RXDR_RXDATA_Pos (0U)
9493 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
9494 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
9496 /****************** Bit definition for I2C_TXDR register *********************/
9497 #define I2C_TXDR_TXDATA_Pos (0U)
9498 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
9499 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
9501 /******************************************************************************/
9502 /* */
9503 /* Independent WATCHDOG */
9504 /* */
9505 /******************************************************************************/
9506 /******************* Bit definition for IWDG_KR register ********************/
9507 #define IWDG_KR_KEY_Pos (0U)
9508 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9509 #define IWDG_KR_KEY IWDG_KR_KEY_Msk
9511 /******************* Bit definition for IWDG_PR register ********************/
9512 #define IWDG_PR_PR_Pos (0U)
9513 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9514 #define IWDG_PR_PR IWDG_PR_PR_Msk
9515 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9516 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9517 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9519 /******************* Bit definition for IWDG_RLR register *******************/
9520 #define IWDG_RLR_RL_Pos (0U)
9521 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9522 #define IWDG_RLR_RL IWDG_RLR_RL_Msk
9524 /******************* Bit definition for IWDG_SR register ********************/
9525 #define IWDG_SR_PVU_Pos (0U)
9526 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9527 #define IWDG_SR_PVU IWDG_SR_PVU_Msk
9528 #define IWDG_SR_RVU_Pos (1U)
9529 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9530 #define IWDG_SR_RVU IWDG_SR_RVU_Msk
9531 #define IWDG_SR_WVU_Pos (2U)
9532 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
9533 #define IWDG_SR_WVU IWDG_SR_WVU_Msk
9535 /******************* Bit definition for IWDG_KR register ********************/
9536 #define IWDG_WINR_WIN_Pos (0U)
9537 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
9538 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
9540 /******************************************************************************/
9541 /* */
9542 /* Firewall */
9543 /* */
9544 /******************************************************************************/
9545 
9546 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
9547 #define FW_CSSA_ADD_Pos (8U)
9548 #define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos)
9549 #define FW_CSSA_ADD FW_CSSA_ADD_Msk
9550 #define FW_CSL_LENG_Pos (8U)
9551 #define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos)
9552 #define FW_CSL_LENG FW_CSL_LENG_Msk
9553 #define FW_NVDSSA_ADD_Pos (8U)
9554 #define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos)
9555 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk
9556 #define FW_NVDSL_LENG_Pos (8U)
9557 #define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos)
9558 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk
9559 #define FW_VDSSA_ADD_Pos (6U)
9560 #define FW_VDSSA_ADD_Msk (0x7FFUL << FW_VDSSA_ADD_Pos)
9561 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk
9562 #define FW_VDSL_LENG_Pos (6U)
9563 #define FW_VDSL_LENG_Msk (0x7FFUL << FW_VDSL_LENG_Pos)
9564 #define FW_VDSL_LENG FW_VDSL_LENG_Msk
9566 /**************************Bit definition for CR register *********************/
9567 #define FW_CR_FPA_Pos (0U)
9568 #define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos)
9569 #define FW_CR_FPA FW_CR_FPA_Msk
9570 #define FW_CR_VDS_Pos (1U)
9571 #define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos)
9572 #define FW_CR_VDS FW_CR_VDS_Msk
9573 #define FW_CR_VDE_Pos (2U)
9574 #define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos)
9575 #define FW_CR_VDE FW_CR_VDE_Msk
9577 /******************************************************************************/
9578 /* */
9579 /* Power Control */
9580 /* */
9581 /******************************************************************************/
9582 
9583 /******************** Bit definition for PWR_CR1 register ********************/
9584 
9585 #define PWR_CR1_LPR_Pos (14U)
9586 #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)
9587 #define PWR_CR1_LPR PWR_CR1_LPR_Msk
9588 #define PWR_CR1_VOS_Pos (9U)
9589 #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
9590 #define PWR_CR1_VOS PWR_CR1_VOS_Msk
9591 #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
9592 #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
9593 #define PWR_CR1_DBP_Pos (8U)
9594 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
9595 #define PWR_CR1_DBP PWR_CR1_DBP_Msk
9596 #define PWR_CR1_LPMS_Pos (0U)
9597 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)
9598 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk
9599 #define PWR_CR1_LPMS_STOP0 (0x00000000UL)
9600 #define PWR_CR1_LPMS_STOP1_Pos (0U)
9601 #define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos)
9602 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk
9603 #define PWR_CR1_LPMS_STOP2_Pos (1U)
9604 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos)
9605 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk
9606 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
9607 #define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)
9608 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk
9609 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
9610 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)
9611 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk
9614 /******************** Bit definition for PWR_CR2 register ********************/
9615 #define PWR_CR2_USV_Pos (10U)
9616 #define PWR_CR2_USV_Msk (0x1UL << PWR_CR2_USV_Pos)
9617 #define PWR_CR2_USV PWR_CR2_USV_Msk
9618 #define PWR_CR2_IOSV_Pos (9U)
9619 #define PWR_CR2_IOSV_Msk (0x1UL << PWR_CR2_IOSV_Pos)
9620 #define PWR_CR2_IOSV PWR_CR2_IOSV_Msk
9622 #define PWR_CR2_PVME_Pos (4U)
9623 #define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos)
9624 #define PWR_CR2_PVME PWR_CR2_PVME_Msk
9625 #define PWR_CR2_PVME4_Pos (7U)
9626 #define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos)
9627 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk
9628 #define PWR_CR2_PVME3_Pos (6U)
9629 #define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos)
9630 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk
9631 #define PWR_CR2_PVME2_Pos (5U)
9632 #define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos)
9633 #define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk
9634 #define PWR_CR2_PVME1_Pos (4U)
9635 #define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos)
9636 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk
9638 #define PWR_CR2_PLS_Pos (1U)
9639 #define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos)
9640 #define PWR_CR2_PLS PWR_CR2_PLS_Msk
9641 #define PWR_CR2_PLS_LEV0 (0x00000000UL)
9642 #define PWR_CR2_PLS_LEV1_Pos (1U)
9643 #define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos)
9644 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk
9645 #define PWR_CR2_PLS_LEV2_Pos (2U)
9646 #define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos)
9647 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk
9648 #define PWR_CR2_PLS_LEV3_Pos (1U)
9649 #define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos)
9650 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk
9651 #define PWR_CR2_PLS_LEV4_Pos (3U)
9652 #define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos)
9653 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk
9654 #define PWR_CR2_PLS_LEV5_Pos (1U)
9655 #define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos)
9656 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk
9657 #define PWR_CR2_PLS_LEV6_Pos (2U)
9658 #define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos)
9659 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk
9660 #define PWR_CR2_PLS_LEV7_Pos (1U)
9661 #define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos)
9662 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk
9663 #define PWR_CR2_PVDE_Pos (0U)
9664 #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos)
9665 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk
9667 /******************** Bit definition for PWR_CR3 register ********************/
9668 #define PWR_CR3_EIWUL_Pos (15U)
9669 #define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos)
9670 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk
9671 #define PWR_CR3_APC_Pos (10U)
9672 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)
9673 #define PWR_CR3_APC PWR_CR3_APC_Msk
9674 #define PWR_CR3_RRS_Pos (8U)
9675 #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos)
9676 #define PWR_CR3_RRS PWR_CR3_RRS_Msk
9677 #define PWR_CR3_EWUP5_Pos (4U)
9678 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos)
9679 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk
9680 #define PWR_CR3_EWUP4_Pos (3U)
9681 #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)
9682 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk
9683 #define PWR_CR3_EWUP3_Pos (2U)
9684 #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos)
9685 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk
9686 #define PWR_CR3_EWUP2_Pos (1U)
9687 #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)
9688 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk
9689 #define PWR_CR3_EWUP1_Pos (0U)
9690 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)
9691 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk
9692 #define PWR_CR3_EWUP_Pos (0U)
9693 #define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos)
9694 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk
9696 /* Legacy defines */
9697 #define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
9698 #define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
9699 #define PWR_CR3_EIWF PWR_CR3_EIWUL
9700 
9701 
9702 /******************** Bit definition for PWR_CR4 register ********************/
9703 #define PWR_CR4_VBRS_Pos (9U)
9704 #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)
9705 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk
9706 #define PWR_CR4_VBE_Pos (8U)
9707 #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)
9708 #define PWR_CR4_VBE PWR_CR4_VBE_Msk
9709 #define PWR_CR4_WP5_Pos (4U)
9710 #define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos)
9711 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk
9712 #define PWR_CR4_WP4_Pos (3U)
9713 #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)
9714 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk
9715 #define PWR_CR4_WP3_Pos (2U)
9716 #define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos)
9717 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk
9718 #define PWR_CR4_WP2_Pos (1U)
9719 #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)
9720 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk
9721 #define PWR_CR4_WP1_Pos (0U)
9722 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)
9723 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk
9725 /******************** Bit definition for PWR_SR1 register ********************/
9726 #define PWR_SR1_WUFI_Pos (15U)
9727 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)
9728 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk
9729 #define PWR_SR1_SBF_Pos (8U)
9730 #define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)
9731 #define PWR_SR1_SBF PWR_SR1_SBF_Msk
9732 #define PWR_SR1_WUF_Pos (0U)
9733 #define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos)
9734 #define PWR_SR1_WUF PWR_SR1_WUF_Msk
9735 #define PWR_SR1_WUF5_Pos (4U)
9736 #define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos)
9737 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk
9738 #define PWR_SR1_WUF4_Pos (3U)
9739 #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)
9740 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk
9741 #define PWR_SR1_WUF3_Pos (2U)
9742 #define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos)
9743 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk
9744 #define PWR_SR1_WUF2_Pos (1U)
9745 #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)
9746 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk
9747 #define PWR_SR1_WUF1_Pos (0U)
9748 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)
9749 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk
9751 /******************** Bit definition for PWR_SR2 register ********************/
9752 #define PWR_SR2_PVMO4_Pos (15U)
9753 #define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos)
9754 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk
9755 #define PWR_SR2_PVMO3_Pos (14U)
9756 #define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos)
9757 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk
9758 #define PWR_SR2_PVMO2_Pos (13U)
9759 #define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos)
9760 #define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk
9761 #define PWR_SR2_PVMO1_Pos (12U)
9762 #define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos)
9763 #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk
9764 #define PWR_SR2_PVDO_Pos (11U)
9765 #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos)
9766 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk
9767 #define PWR_SR2_VOSF_Pos (10U)
9768 #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)
9769 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk
9770 #define PWR_SR2_REGLPF_Pos (9U)
9771 #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)
9772 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk
9773 #define PWR_SR2_REGLPS_Pos (8U)
9774 #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)
9775 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk
9777 /******************** Bit definition for PWR_SCR register ********************/
9778 #define PWR_SCR_CSBF_Pos (8U)
9779 #define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)
9780 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk
9781 #define PWR_SCR_CWUF_Pos (0U)
9782 #define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos)
9783 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk
9784 #define PWR_SCR_CWUF5_Pos (4U)
9785 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos)
9786 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk
9787 #define PWR_SCR_CWUF4_Pos (3U)
9788 #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)
9789 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk
9790 #define PWR_SCR_CWUF3_Pos (2U)
9791 #define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos)
9792 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk
9793 #define PWR_SCR_CWUF2_Pos (1U)
9794 #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)
9795 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk
9796 #define PWR_SCR_CWUF1_Pos (0U)
9797 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)
9798 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk
9800 /******************** Bit definition for PWR_PUCRA register ********************/
9801 #define PWR_PUCRA_PA15_Pos (15U)
9802 #define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos)
9803 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk
9804 #define PWR_PUCRA_PA13_Pos (13U)
9805 #define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos)
9806 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk
9807 #define PWR_PUCRA_PA12_Pos (12U)
9808 #define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos)
9809 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk
9810 #define PWR_PUCRA_PA11_Pos (11U)
9811 #define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos)
9812 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk
9813 #define PWR_PUCRA_PA10_Pos (10U)
9814 #define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos)
9815 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk
9816 #define PWR_PUCRA_PA9_Pos (9U)
9817 #define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos)
9818 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk
9819 #define PWR_PUCRA_PA8_Pos (8U)
9820 #define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos)
9821 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk
9822 #define PWR_PUCRA_PA7_Pos (7U)
9823 #define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos)
9824 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk
9825 #define PWR_PUCRA_PA6_Pos (6U)
9826 #define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos)
9827 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk
9828 #define PWR_PUCRA_PA5_Pos (5U)
9829 #define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos)
9830 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk
9831 #define PWR_PUCRA_PA4_Pos (4U)
9832 #define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos)
9833 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk
9834 #define PWR_PUCRA_PA3_Pos (3U)
9835 #define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos)
9836 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk
9837 #define PWR_PUCRA_PA2_Pos (2U)
9838 #define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos)
9839 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk
9840 #define PWR_PUCRA_PA1_Pos (1U)
9841 #define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos)
9842 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk
9843 #define PWR_PUCRA_PA0_Pos (0U)
9844 #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos)
9845 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk
9847 /******************** Bit definition for PWR_PDCRA register ********************/
9848 #define PWR_PDCRA_PA14_Pos (14U)
9849 #define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos)
9850 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk
9851 #define PWR_PDCRA_PA12_Pos (12U)
9852 #define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos)
9853 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk
9854 #define PWR_PDCRA_PA11_Pos (11U)
9855 #define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos)
9856 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk
9857 #define PWR_PDCRA_PA10_Pos (10U)
9858 #define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos)
9859 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk
9860 #define PWR_PDCRA_PA9_Pos (9U)
9861 #define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos)
9862 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk
9863 #define PWR_PDCRA_PA8_Pos (8U)
9864 #define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos)
9865 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk
9866 #define PWR_PDCRA_PA7_Pos (7U)
9867 #define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos)
9868 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk
9869 #define PWR_PDCRA_PA6_Pos (6U)
9870 #define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos)
9871 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk
9872 #define PWR_PDCRA_PA5_Pos (5U)
9873 #define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos)
9874 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk
9875 #define PWR_PDCRA_PA4_Pos (4U)
9876 #define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos)
9877 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk
9878 #define PWR_PDCRA_PA3_Pos (3U)
9879 #define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos)
9880 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk
9881 #define PWR_PDCRA_PA2_Pos (2U)
9882 #define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos)
9883 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk
9884 #define PWR_PDCRA_PA1_Pos (1U)
9885 #define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos)
9886 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk
9887 #define PWR_PDCRA_PA0_Pos (0U)
9888 #define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos)
9889 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk
9891 /******************** Bit definition for PWR_PUCRB register ********************/
9892 #define PWR_PUCRB_PB15_Pos (15U)
9893 #define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos)
9894 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk
9895 #define PWR_PUCRB_PB14_Pos (14U)
9896 #define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos)
9897 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk
9898 #define PWR_PUCRB_PB13_Pos (13U)
9899 #define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos)
9900 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk
9901 #define PWR_PUCRB_PB12_Pos (12U)
9902 #define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos)
9903 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk
9904 #define PWR_PUCRB_PB11_Pos (11U)
9905 #define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos)
9906 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk
9907 #define PWR_PUCRB_PB10_Pos (10U)
9908 #define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos)
9909 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk
9910 #define PWR_PUCRB_PB9_Pos (9U)
9911 #define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos)
9912 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk
9913 #define PWR_PUCRB_PB8_Pos (8U)
9914 #define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos)
9915 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk
9916 #define PWR_PUCRB_PB7_Pos (7U)
9917 #define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos)
9918 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk
9919 #define PWR_PUCRB_PB6_Pos (6U)
9920 #define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos)
9921 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk
9922 #define PWR_PUCRB_PB5_Pos (5U)
9923 #define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos)
9924 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk
9925 #define PWR_PUCRB_PB4_Pos (4U)
9926 #define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos)
9927 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk
9928 #define PWR_PUCRB_PB3_Pos (3U)
9929 #define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos)
9930 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk
9931 #define PWR_PUCRB_PB2_Pos (2U)
9932 #define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos)
9933 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk
9934 #define PWR_PUCRB_PB1_Pos (1U)
9935 #define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos)
9936 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk
9937 #define PWR_PUCRB_PB0_Pos (0U)
9938 #define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos)
9939 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk
9941 /******************** Bit definition for PWR_PDCRB register ********************/
9942 #define PWR_PDCRB_PB15_Pos (15U)
9943 #define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos)
9944 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk
9945 #define PWR_PDCRB_PB14_Pos (14U)
9946 #define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos)
9947 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk
9948 #define PWR_PDCRB_PB13_Pos (13U)
9949 #define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos)
9950 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk
9951 #define PWR_PDCRB_PB12_Pos (12U)
9952 #define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos)
9953 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk
9954 #define PWR_PDCRB_PB11_Pos (11U)
9955 #define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos)
9956 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk
9957 #define PWR_PDCRB_PB10_Pos (10U)
9958 #define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos)
9959 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk
9960 #define PWR_PDCRB_PB9_Pos (9U)
9961 #define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos)
9962 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk
9963 #define PWR_PDCRB_PB8_Pos (8U)
9964 #define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos)
9965 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk
9966 #define PWR_PDCRB_PB7_Pos (7U)
9967 #define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos)
9968 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk
9969 #define PWR_PDCRB_PB6_Pos (6U)
9970 #define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos)
9971 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk
9972 #define PWR_PDCRB_PB5_Pos (5U)
9973 #define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos)
9974 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk
9975 #define PWR_PDCRB_PB3_Pos (3U)
9976 #define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos)
9977 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk
9978 #define PWR_PDCRB_PB2_Pos (2U)
9979 #define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos)
9980 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk
9981 #define PWR_PDCRB_PB1_Pos (1U)
9982 #define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos)
9983 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk
9984 #define PWR_PDCRB_PB0_Pos (0U)
9985 #define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos)
9986 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk
9988 /******************** Bit definition for PWR_PUCRC register ********************/
9989 #define PWR_PUCRC_PC15_Pos (15U)
9990 #define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos)
9991 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk
9992 #define PWR_PUCRC_PC14_Pos (14U)
9993 #define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos)
9994 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk
9995 #define PWR_PUCRC_PC13_Pos (13U)
9996 #define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos)
9997 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk
9998 #define PWR_PUCRC_PC12_Pos (12U)
9999 #define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos)
10000 #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk
10001 #define PWR_PUCRC_PC11_Pos (11U)
10002 #define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos)
10003 #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk
10004 #define PWR_PUCRC_PC10_Pos (10U)
10005 #define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos)
10006 #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk
10007 #define PWR_PUCRC_PC9_Pos (9U)
10008 #define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos)
10009 #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk
10010 #define PWR_PUCRC_PC8_Pos (8U)
10011 #define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos)
10012 #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk
10013 #define PWR_PUCRC_PC7_Pos (7U)
10014 #define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos)
10015 #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk
10016 #define PWR_PUCRC_PC6_Pos (6U)
10017 #define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos)
10018 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk
10019 #define PWR_PUCRC_PC5_Pos (5U)
10020 #define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos)
10021 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk
10022 #define PWR_PUCRC_PC4_Pos (4U)
10023 #define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos)
10024 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk
10025 #define PWR_PUCRC_PC3_Pos (3U)
10026 #define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos)
10027 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk
10028 #define PWR_PUCRC_PC2_Pos (2U)
10029 #define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos)
10030 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk
10031 #define PWR_PUCRC_PC1_Pos (1U)
10032 #define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos)
10033 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk
10034 #define PWR_PUCRC_PC0_Pos (0U)
10035 #define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos)
10036 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk
10038 /******************** Bit definition for PWR_PDCRC register ********************/
10039 #define PWR_PDCRC_PC15_Pos (15U)
10040 #define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos)
10041 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk
10042 #define PWR_PDCRC_PC14_Pos (14U)
10043 #define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos)
10044 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk
10045 #define PWR_PDCRC_PC13_Pos (13U)
10046 #define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos)
10047 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk
10048 #define PWR_PDCRC_PC12_Pos (12U)
10049 #define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos)
10050 #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk
10051 #define PWR_PDCRC_PC11_Pos (11U)
10052 #define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos)
10053 #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk
10054 #define PWR_PDCRC_PC10_Pos (10U)
10055 #define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos)
10056 #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk
10057 #define PWR_PDCRC_PC9_Pos (9U)
10058 #define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos)
10059 #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk
10060 #define PWR_PDCRC_PC8_Pos (8U)
10061 #define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos)
10062 #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk
10063 #define PWR_PDCRC_PC7_Pos (7U)
10064 #define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos)
10065 #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk
10066 #define PWR_PDCRC_PC6_Pos (6U)
10067 #define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos)
10068 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk
10069 #define PWR_PDCRC_PC5_Pos (5U)
10070 #define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos)
10071 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk
10072 #define PWR_PDCRC_PC4_Pos (4U)
10073 #define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos)
10074 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk
10075 #define PWR_PDCRC_PC3_Pos (3U)
10076 #define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos)
10077 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk
10078 #define PWR_PDCRC_PC2_Pos (2U)
10079 #define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos)
10080 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk
10081 #define PWR_PDCRC_PC1_Pos (1U)
10082 #define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos)
10083 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk
10084 #define PWR_PDCRC_PC0_Pos (0U)
10085 #define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos)
10086 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk
10088 /******************** Bit definition for PWR_PUCRD register ********************/
10089 #define PWR_PUCRD_PD15_Pos (15U)
10090 #define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos)
10091 #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk
10092 #define PWR_PUCRD_PD14_Pos (14U)
10093 #define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos)
10094 #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk
10095 #define PWR_PUCRD_PD13_Pos (13U)
10096 #define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos)
10097 #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk
10098 #define PWR_PUCRD_PD12_Pos (12U)
10099 #define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos)
10100 #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk
10101 #define PWR_PUCRD_PD11_Pos (11U)
10102 #define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos)
10103 #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk
10104 #define PWR_PUCRD_PD10_Pos (10U)
10105 #define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos)
10106 #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk
10107 #define PWR_PUCRD_PD9_Pos (9U)
10108 #define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos)
10109 #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk
10110 #define PWR_PUCRD_PD8_Pos (8U)
10111 #define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos)
10112 #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk
10113 #define PWR_PUCRD_PD7_Pos (7U)
10114 #define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos)
10115 #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk
10116 #define PWR_PUCRD_PD6_Pos (6U)
10117 #define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos)
10118 #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk
10119 #define PWR_PUCRD_PD5_Pos (5U)
10120 #define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos)
10121 #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk
10122 #define PWR_PUCRD_PD4_Pos (4U)
10123 #define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos)
10124 #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk
10125 #define PWR_PUCRD_PD3_Pos (3U)
10126 #define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos)
10127 #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk
10128 #define PWR_PUCRD_PD2_Pos (2U)
10129 #define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos)
10130 #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk
10131 #define PWR_PUCRD_PD1_Pos (1U)
10132 #define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos)
10133 #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk
10134 #define PWR_PUCRD_PD0_Pos (0U)
10135 #define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos)
10136 #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk
10138 /******************** Bit definition for PWR_PDCRD register ********************/
10139 #define PWR_PDCRD_PD15_Pos (15U)
10140 #define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos)
10141 #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk
10142 #define PWR_PDCRD_PD14_Pos (14U)
10143 #define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos)
10144 #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk
10145 #define PWR_PDCRD_PD13_Pos (13U)
10146 #define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos)
10147 #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk
10148 #define PWR_PDCRD_PD12_Pos (12U)
10149 #define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos)
10150 #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk
10151 #define PWR_PDCRD_PD11_Pos (11U)
10152 #define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos)
10153 #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk
10154 #define PWR_PDCRD_PD10_Pos (10U)
10155 #define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos)
10156 #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk
10157 #define PWR_PDCRD_PD9_Pos (9U)
10158 #define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos)
10159 #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk
10160 #define PWR_PDCRD_PD8_Pos (8U)
10161 #define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos)
10162 #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk
10163 #define PWR_PDCRD_PD7_Pos (7U)
10164 #define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos)
10165 #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk
10166 #define PWR_PDCRD_PD6_Pos (6U)
10167 #define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos)
10168 #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk
10169 #define PWR_PDCRD_PD5_Pos (5U)
10170 #define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos)
10171 #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk
10172 #define PWR_PDCRD_PD4_Pos (4U)
10173 #define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos)
10174 #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk
10175 #define PWR_PDCRD_PD3_Pos (3U)
10176 #define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)
10177 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk
10178 #define PWR_PDCRD_PD2_Pos (2U)
10179 #define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)
10180 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk
10181 #define PWR_PDCRD_PD1_Pos (1U)
10182 #define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)
10183 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk
10184 #define PWR_PDCRD_PD0_Pos (0U)
10185 #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)
10186 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk
10188 /******************** Bit definition for PWR_PUCRE register ********************/
10189 #define PWR_PUCRE_PE15_Pos (15U)
10190 #define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos)
10191 #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk
10192 #define PWR_PUCRE_PE14_Pos (14U)
10193 #define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos)
10194 #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk
10195 #define PWR_PUCRE_PE13_Pos (13U)
10196 #define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos)
10197 #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk
10198 #define PWR_PUCRE_PE12_Pos (12U)
10199 #define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos)
10200 #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk
10201 #define PWR_PUCRE_PE11_Pos (11U)
10202 #define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos)
10203 #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk
10204 #define PWR_PUCRE_PE10_Pos (10U)
10205 #define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos)
10206 #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk
10207 #define PWR_PUCRE_PE9_Pos (9U)
10208 #define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos)
10209 #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk
10210 #define PWR_PUCRE_PE8_Pos (8U)
10211 #define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos)
10212 #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk
10213 #define PWR_PUCRE_PE7_Pos (7U)
10214 #define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos)
10215 #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk
10216 #define PWR_PUCRE_PE6_Pos (6U)
10217 #define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos)
10218 #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk
10219 #define PWR_PUCRE_PE5_Pos (5U)
10220 #define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos)
10221 #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk
10222 #define PWR_PUCRE_PE4_Pos (4U)
10223 #define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos)
10224 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk
10225 #define PWR_PUCRE_PE3_Pos (3U)
10226 #define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos)
10227 #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk
10228 #define PWR_PUCRE_PE2_Pos (2U)
10229 #define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos)
10230 #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk
10231 #define PWR_PUCRE_PE1_Pos (1U)
10232 #define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos)
10233 #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk
10234 #define PWR_PUCRE_PE0_Pos (0U)
10235 #define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos)
10236 #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk
10238 /******************** Bit definition for PWR_PDCRE register ********************/
10239 #define PWR_PDCRE_PE15_Pos (15U)
10240 #define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos)
10241 #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk
10242 #define PWR_PDCRE_PE14_Pos (14U)
10243 #define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos)
10244 #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk
10245 #define PWR_PDCRE_PE13_Pos (13U)
10246 #define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos)
10247 #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk
10248 #define PWR_PDCRE_PE12_Pos (12U)
10249 #define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos)
10250 #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk
10251 #define PWR_PDCRE_PE11_Pos (11U)
10252 #define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos)
10253 #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk
10254 #define PWR_PDCRE_PE10_Pos (10U)
10255 #define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos)
10256 #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk
10257 #define PWR_PDCRE_PE9_Pos (9U)
10258 #define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos)
10259 #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk
10260 #define PWR_PDCRE_PE8_Pos (8U)
10261 #define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos)
10262 #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk
10263 #define PWR_PDCRE_PE7_Pos (7U)
10264 #define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos)
10265 #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk
10266 #define PWR_PDCRE_PE6_Pos (6U)
10267 #define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos)
10268 #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk
10269 #define PWR_PDCRE_PE5_Pos (5U)
10270 #define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos)
10271 #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk
10272 #define PWR_PDCRE_PE4_Pos (4U)
10273 #define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos)
10274 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk
10275 #define PWR_PDCRE_PE3_Pos (3U)
10276 #define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos)
10277 #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk
10278 #define PWR_PDCRE_PE2_Pos (2U)
10279 #define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos)
10280 #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk
10281 #define PWR_PDCRE_PE1_Pos (1U)
10282 #define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos)
10283 #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk
10284 #define PWR_PDCRE_PE0_Pos (0U)
10285 #define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos)
10286 #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk
10288 /******************** Bit definition for PWR_PUCRF register ********************/
10289 #define PWR_PUCRF_PF15_Pos (15U)
10290 #define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos)
10291 #define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk
10292 #define PWR_PUCRF_PF14_Pos (14U)
10293 #define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos)
10294 #define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk
10295 #define PWR_PUCRF_PF13_Pos (13U)
10296 #define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos)
10297 #define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk
10298 #define PWR_PUCRF_PF12_Pos (12U)
10299 #define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos)
10300 #define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk
10301 #define PWR_PUCRF_PF11_Pos (11U)
10302 #define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos)
10303 #define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk
10304 #define PWR_PUCRF_PF10_Pos (10U)
10305 #define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos)
10306 #define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk
10307 #define PWR_PUCRF_PF9_Pos (9U)
10308 #define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos)
10309 #define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk
10310 #define PWR_PUCRF_PF8_Pos (8U)
10311 #define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos)
10312 #define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk
10313 #define PWR_PUCRF_PF7_Pos (7U)
10314 #define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos)
10315 #define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk
10316 #define PWR_PUCRF_PF6_Pos (6U)
10317 #define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos)
10318 #define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk
10319 #define PWR_PUCRF_PF5_Pos (5U)
10320 #define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos)
10321 #define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk
10322 #define PWR_PUCRF_PF4_Pos (4U)
10323 #define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos)
10324 #define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk
10325 #define PWR_PUCRF_PF3_Pos (3U)
10326 #define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos)
10327 #define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk
10328 #define PWR_PUCRF_PF2_Pos (2U)
10329 #define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos)
10330 #define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk
10331 #define PWR_PUCRF_PF1_Pos (1U)
10332 #define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos)
10333 #define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk
10334 #define PWR_PUCRF_PF0_Pos (0U)
10335 #define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos)
10336 #define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk
10338 /******************** Bit definition for PWR_PDCRF register ********************/
10339 #define PWR_PDCRF_PF15_Pos (15U)
10340 #define PWR_PDCRF_PF15_Msk (0x1UL << PWR_PDCRF_PF15_Pos)
10341 #define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk
10342 #define PWR_PDCRF_PF14_Pos (14U)
10343 #define PWR_PDCRF_PF14_Msk (0x1UL << PWR_PDCRF_PF14_Pos)
10344 #define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk
10345 #define PWR_PDCRF_PF13_Pos (13U)
10346 #define PWR_PDCRF_PF13_Msk (0x1UL << PWR_PDCRF_PF13_Pos)
10347 #define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk
10348 #define PWR_PDCRF_PF12_Pos (12U)
10349 #define PWR_PDCRF_PF12_Msk (0x1UL << PWR_PDCRF_PF12_Pos)
10350 #define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk
10351 #define PWR_PDCRF_PF11_Pos (11U)
10352 #define PWR_PDCRF_PF11_Msk (0x1UL << PWR_PDCRF_PF11_Pos)
10353 #define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk
10354 #define PWR_PDCRF_PF10_Pos (10U)
10355 #define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos)
10356 #define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk
10357 #define PWR_PDCRF_PF9_Pos (9U)
10358 #define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos)
10359 #define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk
10360 #define PWR_PDCRF_PF8_Pos (8U)
10361 #define PWR_PDCRF_PF8_Msk (0x1UL << PWR_PDCRF_PF8_Pos)
10362 #define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk
10363 #define PWR_PDCRF_PF7_Pos (7U)
10364 #define PWR_PDCRF_PF7_Msk (0x1UL << PWR_PDCRF_PF7_Pos)
10365 #define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk
10366 #define PWR_PDCRF_PF6_Pos (6U)
10367 #define PWR_PDCRF_PF6_Msk (0x1UL << PWR_PDCRF_PF6_Pos)
10368 #define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk
10369 #define PWR_PDCRF_PF5_Pos (5U)
10370 #define PWR_PDCRF_PF5_Msk (0x1UL << PWR_PDCRF_PF5_Pos)
10371 #define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk
10372 #define PWR_PDCRF_PF4_Pos (4U)
10373 #define PWR_PDCRF_PF4_Msk (0x1UL << PWR_PDCRF_PF4_Pos)
10374 #define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk
10375 #define PWR_PDCRF_PF3_Pos (3U)
10376 #define PWR_PDCRF_PF3_Msk (0x1UL << PWR_PDCRF_PF3_Pos)
10377 #define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk
10378 #define PWR_PDCRF_PF2_Pos (2U)
10379 #define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos)
10380 #define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk
10381 #define PWR_PDCRF_PF1_Pos (1U)
10382 #define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos)
10383 #define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk
10384 #define PWR_PDCRF_PF0_Pos (0U)
10385 #define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos)
10386 #define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk
10388 /******************** Bit definition for PWR_PUCRG register ********************/
10389 #define PWR_PUCRG_PG15_Pos (15U)
10390 #define PWR_PUCRG_PG15_Msk (0x1UL << PWR_PUCRG_PG15_Pos)
10391 #define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk
10392 #define PWR_PUCRG_PG14_Pos (14U)
10393 #define PWR_PUCRG_PG14_Msk (0x1UL << PWR_PUCRG_PG14_Pos)
10394 #define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk
10395 #define PWR_PUCRG_PG13_Pos (13U)
10396 #define PWR_PUCRG_PG13_Msk (0x1UL << PWR_PUCRG_PG13_Pos)
10397 #define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk
10398 #define PWR_PUCRG_PG12_Pos (12U)
10399 #define PWR_PUCRG_PG12_Msk (0x1UL << PWR_PUCRG_PG12_Pos)
10400 #define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk
10401 #define PWR_PUCRG_PG11_Pos (11U)
10402 #define PWR_PUCRG_PG11_Msk (0x1UL << PWR_PUCRG_PG11_Pos)
10403 #define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk
10404 #define PWR_PUCRG_PG10_Pos (10U)
10405 #define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos)
10406 #define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk
10407 #define PWR_PUCRG_PG9_Pos (9U)
10408 #define PWR_PUCRG_PG9_Msk (0x1UL << PWR_PUCRG_PG9_Pos)
10409 #define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk
10410 #define PWR_PUCRG_PG8_Pos (8U)
10411 #define PWR_PUCRG_PG8_Msk (0x1UL << PWR_PUCRG_PG8_Pos)
10412 #define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk
10413 #define PWR_PUCRG_PG7_Pos (7U)
10414 #define PWR_PUCRG_PG7_Msk (0x1UL << PWR_PUCRG_PG7_Pos)
10415 #define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk
10416 #define PWR_PUCRG_PG6_Pos (6U)
10417 #define PWR_PUCRG_PG6_Msk (0x1UL << PWR_PUCRG_PG6_Pos)
10418 #define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk
10419 #define PWR_PUCRG_PG5_Pos (5U)
10420 #define PWR_PUCRG_PG5_Msk (0x1UL << PWR_PUCRG_PG5_Pos)
10421 #define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk
10422 #define PWR_PUCRG_PG4_Pos (4U)
10423 #define PWR_PUCRG_PG4_Msk (0x1UL << PWR_PUCRG_PG4_Pos)
10424 #define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk
10425 #define PWR_PUCRG_PG3_Pos (3U)
10426 #define PWR_PUCRG_PG3_Msk (0x1UL << PWR_PUCRG_PG3_Pos)
10427 #define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk
10428 #define PWR_PUCRG_PG2_Pos (2U)
10429 #define PWR_PUCRG_PG2_Msk (0x1UL << PWR_PUCRG_PG2_Pos)
10430 #define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk
10431 #define PWR_PUCRG_PG1_Pos (1U)
10432 #define PWR_PUCRG_PG1_Msk (0x1UL << PWR_PUCRG_PG1_Pos)
10433 #define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk
10434 #define PWR_PUCRG_PG0_Pos (0U)
10435 #define PWR_PUCRG_PG0_Msk (0x1UL << PWR_PUCRG_PG0_Pos)
10436 #define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk
10438 /******************** Bit definition for PWR_PDCRG register ********************/
10439 #define PWR_PDCRG_PG15_Pos (15U)
10440 #define PWR_PDCRG_PG15_Msk (0x1UL << PWR_PDCRG_PG15_Pos)
10441 #define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk
10442 #define PWR_PDCRG_PG14_Pos (14U)
10443 #define PWR_PDCRG_PG14_Msk (0x1UL << PWR_PDCRG_PG14_Pos)
10444 #define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk
10445 #define PWR_PDCRG_PG13_Pos (13U)
10446 #define PWR_PDCRG_PG13_Msk (0x1UL << PWR_PDCRG_PG13_Pos)
10447 #define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk
10448 #define PWR_PDCRG_PG12_Pos (12U)
10449 #define PWR_PDCRG_PG12_Msk (0x1UL << PWR_PDCRG_PG12_Pos)
10450 #define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk
10451 #define PWR_PDCRG_PG11_Pos (11U)
10452 #define PWR_PDCRG_PG11_Msk (0x1UL << PWR_PDCRG_PG11_Pos)
10453 #define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk
10454 #define PWR_PDCRG_PG10_Pos (10U)
10455 #define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos)
10456 #define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk
10457 #define PWR_PDCRG_PG9_Pos (9U)
10458 #define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos)
10459 #define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk
10460 #define PWR_PDCRG_PG8_Pos (8U)
10461 #define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos)
10462 #define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk
10463 #define PWR_PDCRG_PG7_Pos (7U)
10464 #define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos)
10465 #define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk
10466 #define PWR_PDCRG_PG6_Pos (6U)
10467 #define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos)
10468 #define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk
10469 #define PWR_PDCRG_PG5_Pos (5U)
10470 #define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos)
10471 #define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk
10472 #define PWR_PDCRG_PG4_Pos (4U)
10473 #define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos)
10474 #define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk
10475 #define PWR_PDCRG_PG3_Pos (3U)
10476 #define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos)
10477 #define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk
10478 #define PWR_PDCRG_PG2_Pos (2U)
10479 #define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos)
10480 #define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk
10481 #define PWR_PDCRG_PG1_Pos (1U)
10482 #define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos)
10483 #define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk
10484 #define PWR_PDCRG_PG0_Pos (0U)
10485 #define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos)
10486 #define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk
10488 /******************** Bit definition for PWR_PUCRH register ********************/
10489 #define PWR_PUCRH_PH1_Pos (1U)
10490 #define PWR_PUCRH_PH1_Msk (0x1UL << PWR_PUCRH_PH1_Pos)
10491 #define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk
10492 #define PWR_PUCRH_PH0_Pos (0U)
10493 #define PWR_PUCRH_PH0_Msk (0x1UL << PWR_PUCRH_PH0_Pos)
10494 #define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk
10496 /******************** Bit definition for PWR_PDCRH register ********************/
10497 #define PWR_PDCRH_PH1_Pos (1U)
10498 #define PWR_PDCRH_PH1_Msk (0x1UL << PWR_PDCRH_PH1_Pos)
10499 #define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk
10500 #define PWR_PDCRH_PH0_Pos (0U)
10501 #define PWR_PDCRH_PH0_Msk (0x1UL << PWR_PDCRH_PH0_Pos)
10502 #define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk
10505 /******************************************************************************/
10506 /* */
10507 /* Reset and Clock Control */
10508 /* */
10509 /******************************************************************************/
10510 /*
10511 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
10512 */
10513 #define RCC_PLLSAI1_SUPPORT
10514 #define RCC_PLLP_SUPPORT
10515 #define RCC_PLLSAI2_SUPPORT
10516 
10517 /******************** Bit definition for RCC_CR register ********************/
10518 #define RCC_CR_MSION_Pos (0U)
10519 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos)
10520 #define RCC_CR_MSION RCC_CR_MSION_Msk
10521 #define RCC_CR_MSIRDY_Pos (1U)
10522 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos)
10523 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk
10524 #define RCC_CR_MSIPLLEN_Pos (2U)
10525 #define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos)
10526 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk
10527 #define RCC_CR_MSIRGSEL_Pos (3U)
10528 #define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos)
10529 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk
10532 #define RCC_CR_MSIRANGE_Pos (4U)
10533 #define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos)
10534 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk
10535 #define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos)
10536 #define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos)
10537 #define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos)
10538 #define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos)
10539 #define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos)
10540 #define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos)
10541 #define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos)
10542 #define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos)
10543 #define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos)
10544 #define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos)
10545 #define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos)
10546 #define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos)
10548 #define RCC_CR_HSION_Pos (8U)
10549 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
10550 #define RCC_CR_HSION RCC_CR_HSION_Msk
10551 #define RCC_CR_HSIKERON_Pos (9U)
10552 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
10553 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
10554 #define RCC_CR_HSIRDY_Pos (10U)
10555 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
10556 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10557 #define RCC_CR_HSIASFS_Pos (11U)
10558 #define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos)
10559 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk
10561 #define RCC_CR_HSEON_Pos (16U)
10562 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
10563 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
10564 #define RCC_CR_HSERDY_Pos (17U)
10565 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
10566 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10567 #define RCC_CR_HSEBYP_Pos (18U)
10568 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
10569 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10570 #define RCC_CR_CSSON_Pos (19U)
10571 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
10572 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
10574 #define RCC_CR_PLLON_Pos (24U)
10575 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
10576 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
10577 #define RCC_CR_PLLRDY_Pos (25U)
10578 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
10579 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10580 #define RCC_CR_PLLSAI1ON_Pos (26U)
10581 #define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos)
10582 #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk
10583 #define RCC_CR_PLLSAI1RDY_Pos (27U)
10584 #define RCC_CR_PLLSAI1RDY_Msk (0x1UL << RCC_CR_PLLSAI1RDY_Pos)
10585 #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk
10586 #define RCC_CR_PLLSAI2ON_Pos (28U)
10587 #define RCC_CR_PLLSAI2ON_Msk (0x1UL << RCC_CR_PLLSAI2ON_Pos)
10588 #define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk
10589 #define RCC_CR_PLLSAI2RDY_Pos (29U)
10590 #define RCC_CR_PLLSAI2RDY_Msk (0x1UL << RCC_CR_PLLSAI2RDY_Pos)
10591 #define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk
10593 /******************** Bit definition for RCC_ICSCR register ***************/
10594 
10595 #define RCC_ICSCR_MSICAL_Pos (0U)
10596 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos)
10597 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk
10598 #define RCC_ICSCR_MSICAL_0 (0x01UL << RCC_ICSCR_MSICAL_Pos)
10599 #define RCC_ICSCR_MSICAL_1 (0x02UL << RCC_ICSCR_MSICAL_Pos)
10600 #define RCC_ICSCR_MSICAL_2 (0x04UL << RCC_ICSCR_MSICAL_Pos)
10601 #define RCC_ICSCR_MSICAL_3 (0x08UL << RCC_ICSCR_MSICAL_Pos)
10602 #define RCC_ICSCR_MSICAL_4 (0x10UL << RCC_ICSCR_MSICAL_Pos)
10603 #define RCC_ICSCR_MSICAL_5 (0x20UL << RCC_ICSCR_MSICAL_Pos)
10604 #define RCC_ICSCR_MSICAL_6 (0x40UL << RCC_ICSCR_MSICAL_Pos)
10605 #define RCC_ICSCR_MSICAL_7 (0x80UL << RCC_ICSCR_MSICAL_Pos)
10608 #define RCC_ICSCR_MSITRIM_Pos (8U)
10609 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos)
10610 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk
10611 #define RCC_ICSCR_MSITRIM_0 (0x01UL << RCC_ICSCR_MSITRIM_Pos)
10612 #define RCC_ICSCR_MSITRIM_1 (0x02UL << RCC_ICSCR_MSITRIM_Pos)
10613 #define RCC_ICSCR_MSITRIM_2 (0x04UL << RCC_ICSCR_MSITRIM_Pos)
10614 #define RCC_ICSCR_MSITRIM_3 (0x08UL << RCC_ICSCR_MSITRIM_Pos)
10615 #define RCC_ICSCR_MSITRIM_4 (0x10UL << RCC_ICSCR_MSITRIM_Pos)
10616 #define RCC_ICSCR_MSITRIM_5 (0x20UL << RCC_ICSCR_MSITRIM_Pos)
10617 #define RCC_ICSCR_MSITRIM_6 (0x40UL << RCC_ICSCR_MSITRIM_Pos)
10618 #define RCC_ICSCR_MSITRIM_7 (0x80UL << RCC_ICSCR_MSITRIM_Pos)
10621 #define RCC_ICSCR_HSICAL_Pos (16U)
10622 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)
10623 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk
10624 #define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)
10625 #define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)
10626 #define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)
10627 #define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)
10628 #define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)
10629 #define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)
10630 #define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)
10631 #define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)
10634 #define RCC_ICSCR_HSITRIM_Pos (24U)
10635 #define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos)
10636 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk
10637 #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)
10638 #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)
10639 #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)
10640 #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)
10641 #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)
10643 /******************** Bit definition for RCC_CFGR register ******************/
10644 
10645 #define RCC_CFGR_SW_Pos (0U)
10646 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
10647 #define RCC_CFGR_SW RCC_CFGR_SW_Msk
10648 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
10649 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
10651 #define RCC_CFGR_SW_MSI (0x00000000UL)
10652 #define RCC_CFGR_SW_HSI (0x00000001UL)
10653 #define RCC_CFGR_SW_HSE (0x00000002UL)
10654 #define RCC_CFGR_SW_PLL (0x00000003UL)
10657 #define RCC_CFGR_SWS_Pos (2U)
10658 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
10659 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
10660 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
10661 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
10663 #define RCC_CFGR_SWS_MSI (0x00000000UL)
10664 #define RCC_CFGR_SWS_HSI (0x00000004UL)
10665 #define RCC_CFGR_SWS_HSE (0x00000008UL)
10666 #define RCC_CFGR_SWS_PLL (0x0000000CUL)
10669 #define RCC_CFGR_HPRE_Pos (4U)
10670 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
10671 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
10672 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
10673 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
10674 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
10675 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
10677 #define RCC_CFGR_HPRE_DIV1 (0x00000000UL)
10678 #define RCC_CFGR_HPRE_DIV2 (0x00000080UL)
10679 #define RCC_CFGR_HPRE_DIV4 (0x00000090UL)
10680 #define RCC_CFGR_HPRE_DIV8 (0x000000A0UL)
10681 #define RCC_CFGR_HPRE_DIV16 (0x000000B0UL)
10682 #define RCC_CFGR_HPRE_DIV64 (0x000000C0UL)
10683 #define RCC_CFGR_HPRE_DIV128 (0x000000D0UL)
10684 #define RCC_CFGR_HPRE_DIV256 (0x000000E0UL)
10685 #define RCC_CFGR_HPRE_DIV512 (0x000000F0UL)
10688 #define RCC_CFGR_PPRE1_Pos (8U)
10689 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
10690 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
10691 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
10692 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
10693 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
10695 #define RCC_CFGR_PPRE1_DIV1 (0x00000000UL)
10696 #define RCC_CFGR_PPRE1_DIV2 (0x00000400UL)
10697 #define RCC_CFGR_PPRE1_DIV4 (0x00000500UL)
10698 #define RCC_CFGR_PPRE1_DIV8 (0x00000600UL)
10699 #define RCC_CFGR_PPRE1_DIV16 (0x00000700UL)
10702 #define RCC_CFGR_PPRE2_Pos (11U)
10703 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
10704 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
10705 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
10706 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
10707 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
10709 #define RCC_CFGR_PPRE2_DIV1 (0x00000000UL)
10710 #define RCC_CFGR_PPRE2_DIV2 (0x00002000UL)
10711 #define RCC_CFGR_PPRE2_DIV4 (0x00002800UL)
10712 #define RCC_CFGR_PPRE2_DIV8 (0x00003000UL)
10713 #define RCC_CFGR_PPRE2_DIV16 (0x00003800UL)
10715 #define RCC_CFGR_STOPWUCK_Pos (15U)
10716 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
10717 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
10720 #define RCC_CFGR_MCOSEL_Pos (24U)
10721 #define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos)
10722 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk
10723 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)
10724 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)
10725 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)
10727 #define RCC_CFGR_MCOPRE_Pos (28U)
10728 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)
10729 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk
10730 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)
10731 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)
10732 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)
10734 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000UL)
10735 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000UL)
10736 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000UL)
10737 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000UL)
10738 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000UL)
10740 /* Legacy aliases */
10741 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
10742 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
10743 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
10744 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
10745 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
10746 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
10747 
10748 /******************** Bit definition for RCC_PLLCFGR register ***************/
10749 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
10750 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)
10751 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10752 
10753 #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
10754 #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos)
10755 #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk
10756 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
10757 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)
10758 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk
10759 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
10760 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
10761 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10763 #define RCC_PLLCFGR_PLLM_Pos (4U)
10764 #define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos)
10765 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10766 #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)
10767 #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)
10768 #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)
10770 #define RCC_PLLCFGR_PLLN_Pos (8U)
10771 #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)
10772 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10773 #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)
10774 #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)
10775 #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)
10776 #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)
10777 #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)
10778 #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)
10779 #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)
10781 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
10782 #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)
10783 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
10784 #define RCC_PLLCFGR_PLLP_Pos (17U)
10785 #define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos)
10786 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10787 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
10788 #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)
10789 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
10790 
10791 #define RCC_PLLCFGR_PLLQ_Pos (21U)
10792 #define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos)
10793 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10794 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
10795 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
10797 #define RCC_PLLCFGR_PLLREN_Pos (24U)
10798 #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)
10799 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
10800 #define RCC_PLLCFGR_PLLR_Pos (25U)
10801 #define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos)
10802 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
10803 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
10804 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
10806 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
10807 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
10808 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10809 #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
10810 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10811 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10812 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10813 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10814 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10815 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10816 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10818 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
10819 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos)
10820 #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
10821 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
10822 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
10823 #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
10824 
10825 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
10826 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos)
10827 #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
10828 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
10829 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
10830 #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
10831 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
10832 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
10834 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
10835 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos)
10836 #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
10837 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
10838 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
10839 #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
10840 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
10841 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
10843 /******************** Bit definition for RCC_PLLSAI2CFGR register ************/
10844 #define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
10845 #define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FUL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10846 #define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
10847 #define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10848 #define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10849 #define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10850 #define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10851 #define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10852 #define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10853 #define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10855 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
10856 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos)
10857 #define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
10858 #define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
10859 #define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
10860 #define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
10861 
10862 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
10863 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos)
10864 #define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
10865 #define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
10866 #define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
10867 #define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
10868 #define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
10869 #define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
10871 /******************** Bit definition for RCC_CIER register ******************/
10872 #define RCC_CIER_LSIRDYIE_Pos (0U)
10873 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
10874 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
10875 #define RCC_CIER_LSERDYIE_Pos (1U)
10876 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
10877 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
10878 #define RCC_CIER_MSIRDYIE_Pos (2U)
10879 #define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos)
10880 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
10881 #define RCC_CIER_HSIRDYIE_Pos (3U)
10882 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
10883 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
10884 #define RCC_CIER_HSERDYIE_Pos (4U)
10885 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
10886 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
10887 #define RCC_CIER_PLLRDYIE_Pos (5U)
10888 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)
10889 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
10890 #define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
10891 #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos)
10892 #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
10893 #define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
10894 #define RCC_CIER_PLLSAI2RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI2RDYIE_Pos)
10895 #define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
10896 #define RCC_CIER_LSECSSIE_Pos (9U)
10897 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
10898 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
10899 
10900 /******************** Bit definition for RCC_CIFR register ******************/
10901 #define RCC_CIFR_LSIRDYF_Pos (0U)
10902 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
10903 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
10904 #define RCC_CIFR_LSERDYF_Pos (1U)
10905 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
10906 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
10907 #define RCC_CIFR_MSIRDYF_Pos (2U)
10908 #define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos)
10909 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
10910 #define RCC_CIFR_HSIRDYF_Pos (3U)
10911 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
10912 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
10913 #define RCC_CIFR_HSERDYF_Pos (4U)
10914 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
10915 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
10916 #define RCC_CIFR_PLLRDYF_Pos (5U)
10917 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
10918 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
10919 #define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
10920 #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos)
10921 #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
10922 #define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
10923 #define RCC_CIFR_PLLSAI2RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI2RDYF_Pos)
10924 #define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
10925 #define RCC_CIFR_CSSF_Pos (8U)
10926 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)
10927 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
10928 #define RCC_CIFR_LSECSSF_Pos (9U)
10929 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
10930 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
10931 
10932 /******************** Bit definition for RCC_CICR register ******************/
10933 #define RCC_CICR_LSIRDYC_Pos (0U)
10934 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
10935 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
10936 #define RCC_CICR_LSERDYC_Pos (1U)
10937 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
10938 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
10939 #define RCC_CICR_MSIRDYC_Pos (2U)
10940 #define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos)
10941 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
10942 #define RCC_CICR_HSIRDYC_Pos (3U)
10943 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
10944 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
10945 #define RCC_CICR_HSERDYC_Pos (4U)
10946 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
10947 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
10948 #define RCC_CICR_PLLRDYC_Pos (5U)
10949 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
10950 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
10951 #define RCC_CICR_PLLSAI1RDYC_Pos (6U)
10952 #define RCC_CICR_PLLSAI1RDYC_Msk (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos)
10953 #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
10954 #define RCC_CICR_PLLSAI2RDYC_Pos (7U)
10955 #define RCC_CICR_PLLSAI2RDYC_Msk (0x1UL << RCC_CICR_PLLSAI2RDYC_Pos)
10956 #define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
10957 #define RCC_CICR_CSSC_Pos (8U)
10958 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)
10959 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
10960 #define RCC_CICR_LSECSSC_Pos (9U)
10961 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
10962 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
10963 
10964 /******************** Bit definition for RCC_AHB1RSTR register **************/
10965 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
10966 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
10967 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10968 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
10969 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
10970 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10971 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
10972 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)
10973 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
10974 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
10975 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
10976 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10977 #define RCC_AHB1RSTR_TSCRST_Pos (16U)
10978 #define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos)
10979 #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
10980 
10981 /******************** Bit definition for RCC_AHB2RSTR register **************/
10982 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
10983 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)
10984 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
10985 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
10986 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)
10987 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
10988 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
10989 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)
10990 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
10991 #define RCC_AHB2RSTR_GPIODRST_Pos (3U)
10992 #define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)
10993 #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
10994 #define RCC_AHB2RSTR_GPIOERST_Pos (4U)
10995 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)
10996 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
10997 #define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
10998 #define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)
10999 #define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
11000 #define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
11001 #define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)
11002 #define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
11003 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
11004 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)
11005 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
11006 #define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
11007 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
11008 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
11009 #define RCC_AHB2RSTR_ADCRST_Pos (13U)
11010 #define RCC_AHB2RSTR_ADCRST_Msk (0x1UL << RCC_AHB2RSTR_ADCRST_Pos)
11011 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
11012 #define RCC_AHB2RSTR_RNGRST_Pos (18U)
11013 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
11014 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
11015 
11016 /******************** Bit definition for RCC_AHB3RSTR register **************/
11017 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
11018 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
11019 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
11020 #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
11021 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
11022 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
11023 
11024 /******************** Bit definition for RCC_APB1RSTR1 register **************/
11025 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
11026 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)
11027 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
11028 #define RCC_APB1RSTR1_TIM3RST_Pos (1U)
11029 #define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)
11030 #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
11031 #define RCC_APB1RSTR1_TIM4RST_Pos (2U)
11032 #define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)
11033 #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
11034 #define RCC_APB1RSTR1_TIM5RST_Pos (3U)
11035 #define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)
11036 #define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
11037 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
11038 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)
11039 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
11040 #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
11041 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)
11042 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
11043 #define RCC_APB1RSTR1_LCDRST_Pos (9U)
11044 #define RCC_APB1RSTR1_LCDRST_Msk (0x1UL << RCC_APB1RSTR1_LCDRST_Pos)
11045 #define RCC_APB1RSTR1_LCDRST RCC_APB1RSTR1_LCDRST_Msk
11046 #define RCC_APB1RSTR1_SPI2RST_Pos (14U)
11047 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)
11048 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
11049 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
11050 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)
11051 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
11052 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
11053 #define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)
11054 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
11055 #define RCC_APB1RSTR1_USART3RST_Pos (18U)
11056 #define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)
11057 #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
11058 #define RCC_APB1RSTR1_UART4RST_Pos (19U)
11059 #define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)
11060 #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
11061 #define RCC_APB1RSTR1_UART5RST_Pos (20U)
11062 #define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)
11063 #define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
11064 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
11065 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)
11066 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
11067 #define RCC_APB1RSTR1_I2C2RST_Pos (22U)
11068 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)
11069 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
11070 #define RCC_APB1RSTR1_I2C3RST_Pos (23U)
11071 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)
11072 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
11073 #define RCC_APB1RSTR1_CAN1RST_Pos (25U)
11074 #define RCC_APB1RSTR1_CAN1RST_Msk (0x1UL << RCC_APB1RSTR1_CAN1RST_Pos)
11075 #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
11076 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
11077 #define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)
11078 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
11079 #define RCC_APB1RSTR1_DAC1RST_Pos (29U)
11080 #define RCC_APB1RSTR1_DAC1RST_Msk (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos)
11081 #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
11082 #define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
11083 #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos)
11084 #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
11085 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
11086 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)
11087 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
11088 
11089 /******************** Bit definition for RCC_APB1RSTR2 register **************/
11090 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
11091 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)
11092 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
11093 #define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
11094 #define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1UL << RCC_APB1RSTR2_SWPMI1RST_Pos)
11095 #define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
11096 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
11097 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)
11098 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
11099 
11100 /******************** Bit definition for RCC_APB2RSTR register **************/
11101 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
11102 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
11103 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
11104 #define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
11105 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos)
11106 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
11107 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
11108 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
11109 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
11110 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
11111 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
11112 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
11113 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
11114 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
11115 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
11116 #define RCC_APB2RSTR_USART1RST_Pos (14U)
11117 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
11118 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
11119 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
11120 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
11121 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
11122 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
11123 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
11124 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
11125 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
11126 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
11127 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
11128 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
11129 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
11130 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
11131 #define RCC_APB2RSTR_SAI2RST_Pos (22U)
11132 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
11133 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
11134 #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
11135 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
11136 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
11137 
11138 /******************** Bit definition for RCC_AHB1ENR register ***************/
11139 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
11140 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
11141 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11142 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
11143 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
11144 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11145 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
11146 #define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)
11147 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
11148 #define RCC_AHB1ENR_CRCEN_Pos (12U)
11149 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
11150 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11151 #define RCC_AHB1ENR_TSCEN_Pos (16U)
11152 #define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos)
11153 #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
11154 
11155 /******************** Bit definition for RCC_AHB2ENR register ***************/
11156 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
11157 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)
11158 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
11159 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
11160 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)
11161 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
11162 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
11163 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)
11164 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
11165 #define RCC_AHB2ENR_GPIODEN_Pos (3U)
11166 #define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)
11167 #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
11168 #define RCC_AHB2ENR_GPIOEEN_Pos (4U)
11169 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)
11170 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
11171 #define RCC_AHB2ENR_GPIOFEN_Pos (5U)
11172 #define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)
11173 #define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
11174 #define RCC_AHB2ENR_GPIOGEN_Pos (6U)
11175 #define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)
11176 #define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
11177 #define RCC_AHB2ENR_GPIOHEN_Pos (7U)
11178 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)
11179 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
11180 #define RCC_AHB2ENR_OTGFSEN_Pos (12U)
11181 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
11182 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11183 #define RCC_AHB2ENR_ADCEN_Pos (13U)
11184 #define RCC_AHB2ENR_ADCEN_Msk (0x1UL << RCC_AHB2ENR_ADCEN_Pos)
11185 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
11186 #define RCC_AHB2ENR_RNGEN_Pos (18U)
11187 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
11188 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11189 
11190 /******************** Bit definition for RCC_AHB3ENR register ***************/
11191 #define RCC_AHB3ENR_FMCEN_Pos (0U)
11192 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
11193 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11194 #define RCC_AHB3ENR_QSPIEN_Pos (8U)
11195 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
11196 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
11197 
11198 /******************** Bit definition for RCC_APB1ENR1 register ***************/
11199 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
11200 #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)
11201 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
11202 #define RCC_APB1ENR1_TIM3EN_Pos (1U)
11203 #define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)
11204 #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
11205 #define RCC_APB1ENR1_TIM4EN_Pos (2U)
11206 #define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)
11207 #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
11208 #define RCC_APB1ENR1_TIM5EN_Pos (3U)
11209 #define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)
11210 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
11211 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
11212 #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)
11213 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
11214 #define RCC_APB1ENR1_TIM7EN_Pos (5U)
11215 #define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)
11216 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
11217 #define RCC_APB1ENR1_LCDEN_Pos (9U)
11218 #define RCC_APB1ENR1_LCDEN_Msk (0x1UL << RCC_APB1ENR1_LCDEN_Pos)
11219 #define RCC_APB1ENR1_LCDEN RCC_APB1ENR1_LCDEN_Msk
11220 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
11221 #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)
11222 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
11223 #define RCC_APB1ENR1_SPI2EN_Pos (14U)
11224 #define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)
11225 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
11226 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
11227 #define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)
11228 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
11229 #define RCC_APB1ENR1_USART2EN_Pos (17U)
11230 #define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)
11231 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
11232 #define RCC_APB1ENR1_USART3EN_Pos (18U)
11233 #define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)
11234 #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
11235 #define RCC_APB1ENR1_UART4EN_Pos (19U)
11236 #define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)
11237 #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
11238 #define RCC_APB1ENR1_UART5EN_Pos (20U)
11239 #define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)
11240 #define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
11241 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
11242 #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)
11243 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
11244 #define RCC_APB1ENR1_I2C2EN_Pos (22U)
11245 #define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)
11246 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
11247 #define RCC_APB1ENR1_I2C3EN_Pos (23U)
11248 #define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)
11249 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
11250 #define RCC_APB1ENR1_CAN1EN_Pos (25U)
11251 #define RCC_APB1ENR1_CAN1EN_Msk (0x1UL << RCC_APB1ENR1_CAN1EN_Pos)
11252 #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
11253 #define RCC_APB1ENR1_PWREN_Pos (28U)
11254 #define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos)
11255 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
11256 #define RCC_APB1ENR1_DAC1EN_Pos (29U)
11257 #define RCC_APB1ENR1_DAC1EN_Msk (0x1UL << RCC_APB1ENR1_DAC1EN_Pos)
11258 #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
11259 #define RCC_APB1ENR1_OPAMPEN_Pos (30U)
11260 #define RCC_APB1ENR1_OPAMPEN_Msk (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos)
11261 #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
11262 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
11263 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)
11264 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
11265 
11266 /******************** Bit definition for RCC_APB1RSTR2 register **************/
11267 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
11268 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)
11269 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
11270 #define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
11271 #define RCC_APB1ENR2_SWPMI1EN_Msk (0x1UL << RCC_APB1ENR2_SWPMI1EN_Pos)
11272 #define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
11273 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
11274 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)
11275 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
11276 
11277 /******************** Bit definition for RCC_APB2ENR register ***************/
11278 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
11279 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
11280 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11281 #define RCC_APB2ENR_FWEN_Pos (7U)
11282 #define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos)
11283 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
11284 #define RCC_APB2ENR_SDMMC1EN_Pos (10U)
11285 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)
11286 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
11287 #define RCC_APB2ENR_TIM1EN_Pos (11U)
11288 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
11289 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11290 #define RCC_APB2ENR_SPI1EN_Pos (12U)
11291 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
11292 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11293 #define RCC_APB2ENR_TIM8EN_Pos (13U)
11294 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
11295 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11296 #define RCC_APB2ENR_USART1EN_Pos (14U)
11297 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
11298 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11299 #define RCC_APB2ENR_TIM15EN_Pos (16U)
11300 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
11301 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
11302 #define RCC_APB2ENR_TIM16EN_Pos (17U)
11303 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
11304 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
11305 #define RCC_APB2ENR_TIM17EN_Pos (18U)
11306 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
11307 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
11308 #define RCC_APB2ENR_SAI1EN_Pos (21U)
11309 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
11310 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11311 #define RCC_APB2ENR_SAI2EN_Pos (22U)
11312 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
11313 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
11314 #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
11315 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
11316 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
11317 
11318 /******************** Bit definition for RCC_AHB1SMENR register ***************/
11319 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
11320 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)
11321 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
11322 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
11323 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)
11324 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
11325 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
11326 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)
11327 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
11328 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
11329 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)
11330 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
11331 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
11332 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)
11333 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
11334 #define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
11335 #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos)
11336 #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
11337 
11338 /******************** Bit definition for RCC_AHB2SMENR register *************/
11339 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
11340 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)
11341 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
11342 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
11343 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)
11344 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
11345 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
11346 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)
11347 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
11348 #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
11349 #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)
11350 #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
11351 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
11352 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)
11353 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
11354 #define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
11355 #define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)
11356 #define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
11357 #define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
11358 #define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)
11359 #define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
11360 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
11361 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)
11362 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
11363 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
11364 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)
11365 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
11366 #define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
11367 #define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1UL << RCC_AHB2SMENR_OTGFSSMEN_Pos)
11368 #define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
11369 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
11370 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos)
11371 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
11372 #define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
11373 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)
11374 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
11375 
11376 /******************** Bit definition for RCC_AHB3SMENR register *************/
11377 #define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
11378 #define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)
11379 #define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
11380 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
11381 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)
11382 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
11383 
11384 /******************** Bit definition for RCC_APB1SMENR1 register *************/
11385 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
11386 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)
11387 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
11388 #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
11389 #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)
11390 #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
11391 #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
11392 #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)
11393 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
11394 #define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
11395 #define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)
11396 #define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
11397 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
11398 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)
11399 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
11400 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
11401 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)
11402 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
11403 #define RCC_APB1SMENR1_LCDSMEN_Pos (9U)
11404 #define RCC_APB1SMENR1_LCDSMEN_Msk (0x1UL << RCC_APB1SMENR1_LCDSMEN_Pos)
11405 #define RCC_APB1SMENR1_LCDSMEN RCC_APB1SMENR1_LCDSMEN_Msk
11406 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
11407 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)
11408 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
11409 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
11410 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)
11411 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
11412 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
11413 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)
11414 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
11415 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
11416 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)
11417 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
11418 #define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
11419 #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)
11420 #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
11421 #define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
11422 #define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)
11423 #define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
11424 #define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
11425 #define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)
11426 #define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
11427 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
11428 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)
11429 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
11430 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
11431 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)
11432 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
11433 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
11434 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)
11435 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
11436 #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
11437 #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1UL << RCC_APB1SMENR1_CAN1SMEN_Pos)
11438 #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
11439 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
11440 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)
11441 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
11442 #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
11443 #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos)
11444 #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
11445 #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
11446 #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos)
11447 #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
11448 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
11449 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)
11450 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
11451 
11452 /******************** Bit definition for RCC_APB1SMENR2 register *************/
11453 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
11454 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)
11455 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
11456 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
11457 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1UL << RCC_APB1SMENR2_SWPMI1SMEN_Pos)
11458 #define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
11459 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
11460 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)
11461 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
11462 
11463 /******************** Bit definition for RCC_APB2SMENR register *************/
11464 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
11465 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)
11466 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
11467 #define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
11468 #define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1UL << RCC_APB2SMENR_SDMMC1SMEN_Pos)
11469 #define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
11470 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
11471 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)
11472 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
11473 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
11474 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)
11475 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
11476 #define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
11477 #define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)
11478 #define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
11479 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
11480 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)
11481 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
11482 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
11483 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)
11484 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
11485 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
11486 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)
11487 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
11488 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
11489 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)
11490 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
11491 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
11492 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)
11493 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
11494 #define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
11495 #define RCC_APB2SMENR_SAI2SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos)
11496 #define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
11497 #define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
11498 #define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1UL << RCC_APB2SMENR_DFSDM1SMEN_Pos)
11499 #define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
11500 
11501 /******************** Bit definition for RCC_CCIPR register ******************/
11502 #define RCC_CCIPR_USART1SEL_Pos (0U)
11503 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)
11504 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
11505 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)
11506 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)
11508 #define RCC_CCIPR_USART2SEL_Pos (2U)
11509 #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)
11510 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
11511 #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)
11512 #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)
11514 #define RCC_CCIPR_USART3SEL_Pos (4U)
11515 #define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)
11516 #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
11517 #define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)
11518 #define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)
11520 #define RCC_CCIPR_UART4SEL_Pos (6U)
11521 #define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos)
11522 #define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
11523 #define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos)
11524 #define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos)
11526 #define RCC_CCIPR_UART5SEL_Pos (8U)
11527 #define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos)
11528 #define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
11529 #define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos)
11530 #define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos)
11532 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
11533 #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)
11534 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
11535 #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)
11536 #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)
11538 #define RCC_CCIPR_I2C1SEL_Pos (12U)
11539 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)
11540 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
11541 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)
11542 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)
11544 #define RCC_CCIPR_I2C2SEL_Pos (14U)
11545 #define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos)
11546 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
11547 #define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)
11548 #define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)
11550 #define RCC_CCIPR_I2C3SEL_Pos (16U)
11551 #define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)
11552 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
11553 #define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)
11554 #define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)
11556 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
11557 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)
11558 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
11559 #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)
11560 #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)
11562 #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
11563 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)
11564 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
11565 #define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)
11566 #define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)
11568 #define RCC_CCIPR_SAI1SEL_Pos (22U)
11569 #define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)
11570 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
11571 #define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)
11572 #define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)
11574 #define RCC_CCIPR_SAI2SEL_Pos (24U)
11575 #define RCC_CCIPR_SAI2SEL_Msk (0x3UL << RCC_CCIPR_SAI2SEL_Pos)
11576 #define RCC_CCIPR_SAI2SEL RCC_CCIPR_SAI2SEL_Msk
11577 #define RCC_CCIPR_SAI2SEL_0 (0x1UL << RCC_CCIPR_SAI2SEL_Pos)
11578 #define RCC_CCIPR_SAI2SEL_1 (0x2UL << RCC_CCIPR_SAI2SEL_Pos)
11580 #define RCC_CCIPR_CLK48SEL_Pos (26U)
11581 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos)
11582 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
11583 #define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos)
11584 #define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos)
11586 #define RCC_CCIPR_ADCSEL_Pos (28U)
11587 #define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos)
11588 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
11589 #define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos)
11590 #define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos)
11592 #define RCC_CCIPR_SWPMI1SEL_Pos (30U)
11593 #define RCC_CCIPR_SWPMI1SEL_Msk (0x1UL << RCC_CCIPR_SWPMI1SEL_Pos)
11594 #define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
11595 
11596 #define RCC_CCIPR_DFSDM1SEL_Pos (31U)
11597 #define RCC_CCIPR_DFSDM1SEL_Msk (0x1UL << RCC_CCIPR_DFSDM1SEL_Pos)
11598 #define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
11599 
11600 /******************** Bit definition for RCC_BDCR register ******************/
11601 #define RCC_BDCR_LSEON_Pos (0U)
11602 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
11603 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11604 #define RCC_BDCR_LSERDY_Pos (1U)
11605 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
11606 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11607 #define RCC_BDCR_LSEBYP_Pos (2U)
11608 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
11609 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11610 
11611 #define RCC_BDCR_LSEDRV_Pos (3U)
11612 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
11613 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
11614 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
11615 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
11617 #define RCC_BDCR_LSECSSON_Pos (5U)
11618 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
11619 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
11620 #define RCC_BDCR_LSECSSD_Pos (6U)
11621 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
11622 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
11623 
11624 #define RCC_BDCR_RTCSEL_Pos (8U)
11625 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
11626 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11627 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
11628 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
11630 #define RCC_BDCR_RTCEN_Pos (15U)
11631 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
11632 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11633 #define RCC_BDCR_BDRST_Pos (16U)
11634 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
11635 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11636 #define RCC_BDCR_LSCOEN_Pos (24U)
11637 #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)
11638 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
11639 #define RCC_BDCR_LSCOSEL_Pos (25U)
11640 #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)
11641 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
11642 
11643 /******************** Bit definition for RCC_CSR register *******************/
11644 #define RCC_CSR_LSION_Pos (0U)
11645 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
11646 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
11647 #define RCC_CSR_LSIRDY_Pos (1U)
11648 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
11649 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11650 
11651 #define RCC_CSR_MSISRANGE_Pos (8U)
11652 #define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos)
11653 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
11654 #define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos)
11655 #define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos)
11656 #define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos)
11657 #define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos)
11659 #define RCC_CSR_RMVF_Pos (23U)
11660 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
11661 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11662 #define RCC_CSR_FWRSTF_Pos (24U)
11663 #define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos)
11664 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
11665 #define RCC_CSR_OBLRSTF_Pos (25U)
11666 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)
11667 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
11668 #define RCC_CSR_PINRSTF_Pos (26U)
11669 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
11670 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11671 #define RCC_CSR_BORRSTF_Pos (27U)
11672 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
11673 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11674 #define RCC_CSR_SFTRSTF_Pos (28U)
11675 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
11676 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11677 #define RCC_CSR_IWDGRSTF_Pos (29U)
11678 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
11679 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11680 #define RCC_CSR_WWDGRSTF_Pos (30U)
11681 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
11682 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11683 #define RCC_CSR_LPWRRSTF_Pos (31U)
11684 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
11685 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11686 
11687 /******************************************************************************/
11688 /* */
11689 /* RNG */
11690 /* */
11691 /******************************************************************************/
11692 /******************** Bits definition for RNG_CR register *******************/
11693 #define RNG_CR_RNGEN_Pos (2U)
11694 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
11695 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11696 #define RNG_CR_IE_Pos (3U)
11697 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
11698 #define RNG_CR_IE RNG_CR_IE_Msk
11699 
11700 /******************** Bits definition for RNG_SR register *******************/
11701 #define RNG_SR_DRDY_Pos (0U)
11702 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
11703 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
11704 #define RNG_SR_CECS_Pos (1U)
11705 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
11706 #define RNG_SR_CECS RNG_SR_CECS_Msk
11707 #define RNG_SR_SECS_Pos (2U)
11708 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
11709 #define RNG_SR_SECS RNG_SR_SECS_Msk
11710 #define RNG_SR_CEIS_Pos (5U)
11711 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
11712 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
11713 #define RNG_SR_SEIS_Pos (6U)
11714 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
11715 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
11716 
11717 /******************************************************************************/
11718 /* */
11719 /* Real-Time Clock (RTC) */
11720 /* */
11721 /******************************************************************************/
11722 /*
11723 * @brief Specific device feature definitions
11724 */
11725 #define RTC_TAMPER1_SUPPORT
11726 #define RTC_TAMPER2_SUPPORT
11727 #define RTC_TAMPER3_SUPPORT
11728 #define RTC_WAKEUP_SUPPORT
11729 #define RTC_BACKUP_SUPPORT
11730 
11731 /******************** Bits definition for RTC_TR register *******************/
11732 #define RTC_TR_PM_Pos (22U)
11733 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
11734 #define RTC_TR_PM RTC_TR_PM_Msk
11735 #define RTC_TR_HT_Pos (20U)
11736 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
11737 #define RTC_TR_HT RTC_TR_HT_Msk
11738 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
11739 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
11740 #define RTC_TR_HU_Pos (16U)
11741 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
11742 #define RTC_TR_HU RTC_TR_HU_Msk
11743 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
11744 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
11745 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
11746 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
11747 #define RTC_TR_MNT_Pos (12U)
11748 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
11749 #define RTC_TR_MNT RTC_TR_MNT_Msk
11750 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
11751 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
11752 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
11753 #define RTC_TR_MNU_Pos (8U)
11754 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
11755 #define RTC_TR_MNU RTC_TR_MNU_Msk
11756 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
11757 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
11758 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
11759 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
11760 #define RTC_TR_ST_Pos (4U)
11761 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
11762 #define RTC_TR_ST RTC_TR_ST_Msk
11763 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
11764 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
11765 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
11766 #define RTC_TR_SU_Pos (0U)
11767 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
11768 #define RTC_TR_SU RTC_TR_SU_Msk
11769 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
11770 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
11771 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
11772 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
11774 /******************** Bits definition for RTC_DR register *******************/
11775 #define RTC_DR_YT_Pos (20U)
11776 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
11777 #define RTC_DR_YT RTC_DR_YT_Msk
11778 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
11779 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
11780 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
11781 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
11782 #define RTC_DR_YU_Pos (16U)
11783 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
11784 #define RTC_DR_YU RTC_DR_YU_Msk
11785 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
11786 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
11787 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
11788 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
11789 #define RTC_DR_WDU_Pos (13U)
11790 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
11791 #define RTC_DR_WDU RTC_DR_WDU_Msk
11792 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
11793 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
11794 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
11795 #define RTC_DR_MT_Pos (12U)
11796 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
11797 #define RTC_DR_MT RTC_DR_MT_Msk
11798 #define RTC_DR_MU_Pos (8U)
11799 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
11800 #define RTC_DR_MU RTC_DR_MU_Msk
11801 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
11802 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
11803 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
11804 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
11805 #define RTC_DR_DT_Pos (4U)
11806 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
11807 #define RTC_DR_DT RTC_DR_DT_Msk
11808 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
11809 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
11810 #define RTC_DR_DU_Pos (0U)
11811 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
11812 #define RTC_DR_DU RTC_DR_DU_Msk
11813 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
11814 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
11815 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
11816 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
11818 /******************** Bits definition for RTC_CR register *******************/
11819 #define RTC_CR_ITSE_Pos (24U)
11820 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
11821 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
11822 #define RTC_CR_COE_Pos (23U)
11823 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
11824 #define RTC_CR_COE RTC_CR_COE_Msk
11825 #define RTC_CR_OSEL_Pos (21U)
11826 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
11827 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
11828 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
11829 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
11830 #define RTC_CR_POL_Pos (20U)
11831 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
11832 #define RTC_CR_POL RTC_CR_POL_Msk
11833 #define RTC_CR_COSEL_Pos (19U)
11834 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
11835 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
11836 #define RTC_CR_BKP_Pos (18U)
11837 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
11838 #define RTC_CR_BKP RTC_CR_BKP_Msk
11839 #define RTC_CR_SUB1H_Pos (17U)
11840 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
11841 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11842 #define RTC_CR_ADD1H_Pos (16U)
11843 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
11844 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11845 #define RTC_CR_TSIE_Pos (15U)
11846 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
11847 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
11848 #define RTC_CR_WUTIE_Pos (14U)
11849 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
11850 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11851 #define RTC_CR_ALRBIE_Pos (13U)
11852 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
11853 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11854 #define RTC_CR_ALRAIE_Pos (12U)
11855 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
11856 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11857 #define RTC_CR_TSE_Pos (11U)
11858 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
11859 #define RTC_CR_TSE RTC_CR_TSE_Msk
11860 #define RTC_CR_WUTE_Pos (10U)
11861 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
11862 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
11863 #define RTC_CR_ALRBE_Pos (9U)
11864 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
11865 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11866 #define RTC_CR_ALRAE_Pos (8U)
11867 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
11868 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11869 #define RTC_CR_FMT_Pos (6U)
11870 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
11871 #define RTC_CR_FMT RTC_CR_FMT_Msk
11872 #define RTC_CR_BYPSHAD_Pos (5U)
11873 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
11874 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11875 #define RTC_CR_REFCKON_Pos (4U)
11876 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
11877 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11878 #define RTC_CR_TSEDGE_Pos (3U)
11879 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
11880 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11881 #define RTC_CR_WUCKSEL_Pos (0U)
11882 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
11883 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11884 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
11885 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
11886 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
11888 /* Legacy defines */
11889 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
11890 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
11891 #define RTC_CR_BCK RTC_CR_BKP
11892 
11893 /******************** Bits definition for RTC_ISR register ******************/
11894 #define RTC_ISR_ITSF_Pos (17U)
11895 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
11896 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
11897 #define RTC_ISR_RECALPF_Pos (16U)
11898 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
11899 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11900 #define RTC_ISR_TAMP3F_Pos (15U)
11901 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
11902 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
11903 #define RTC_ISR_TAMP2F_Pos (14U)
11904 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
11905 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11906 #define RTC_ISR_TAMP1F_Pos (13U)
11907 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
11908 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11909 #define RTC_ISR_TSOVF_Pos (12U)
11910 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
11911 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11912 #define RTC_ISR_TSF_Pos (11U)
11913 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
11914 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
11915 #define RTC_ISR_WUTF_Pos (10U)
11916 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
11917 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11918 #define RTC_ISR_ALRBF_Pos (9U)
11919 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
11920 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11921 #define RTC_ISR_ALRAF_Pos (8U)
11922 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
11923 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11924 #define RTC_ISR_INIT_Pos (7U)
11925 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
11926 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
11927 #define RTC_ISR_INITF_Pos (6U)
11928 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
11929 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
11930 #define RTC_ISR_RSF_Pos (5U)
11931 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
11932 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
11933 #define RTC_ISR_INITS_Pos (4U)
11934 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
11935 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
11936 #define RTC_ISR_SHPF_Pos (3U)
11937 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
11938 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11939 #define RTC_ISR_WUTWF_Pos (2U)
11940 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
11941 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11942 #define RTC_ISR_ALRBWF_Pos (1U)
11943 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
11944 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11945 #define RTC_ISR_ALRAWF_Pos (0U)
11946 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
11947 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11948 
11949 /******************** Bits definition for RTC_PRER register *****************/
11950 #define RTC_PRER_PREDIV_A_Pos (16U)
11951 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
11952 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11953 #define RTC_PRER_PREDIV_S_Pos (0U)
11954 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
11955 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11956 
11957 /******************** Bits definition for RTC_WUTR register *****************/
11958 #define RTC_WUTR_WUT_Pos (0U)
11959 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
11960 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11961 
11962 /******************** Bits definition for RTC_ALRMAR register ***************/
11963 #define RTC_ALRMAR_MSK4_Pos (31U)
11964 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
11965 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11966 #define RTC_ALRMAR_WDSEL_Pos (30U)
11967 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
11968 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11969 #define RTC_ALRMAR_DT_Pos (28U)
11970 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
11971 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11972 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
11973 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
11974 #define RTC_ALRMAR_DU_Pos (24U)
11975 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
11976 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11977 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
11978 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
11979 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
11980 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
11981 #define RTC_ALRMAR_MSK3_Pos (23U)
11982 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
11983 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11984 #define RTC_ALRMAR_PM_Pos (22U)
11985 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
11986 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11987 #define RTC_ALRMAR_HT_Pos (20U)
11988 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
11989 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11990 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
11991 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
11992 #define RTC_ALRMAR_HU_Pos (16U)
11993 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
11994 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11995 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
11996 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
11997 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
11998 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
11999 #define RTC_ALRMAR_MSK2_Pos (15U)
12000 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
12001 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
12002 #define RTC_ALRMAR_MNT_Pos (12U)
12003 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
12004 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
12005 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
12006 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
12007 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
12008 #define RTC_ALRMAR_MNU_Pos (8U)
12009 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
12010 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
12011 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
12012 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
12013 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
12014 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
12015 #define RTC_ALRMAR_MSK1_Pos (7U)
12016 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
12017 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
12018 #define RTC_ALRMAR_ST_Pos (4U)
12019 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
12020 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
12021 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
12022 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
12023 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
12024 #define RTC_ALRMAR_SU_Pos (0U)
12025 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
12026 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
12027 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
12028 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
12029 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
12030 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
12032 /******************** Bits definition for RTC_ALRMBR register ***************/
12033 #define RTC_ALRMBR_MSK4_Pos (31U)
12034 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
12035 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
12036 #define RTC_ALRMBR_WDSEL_Pos (30U)
12037 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
12038 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
12039 #define RTC_ALRMBR_DT_Pos (28U)
12040 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
12041 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
12042 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
12043 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
12044 #define RTC_ALRMBR_DU_Pos (24U)
12045 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
12046 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
12047 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
12048 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
12049 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
12050 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
12051 #define RTC_ALRMBR_MSK3_Pos (23U)
12052 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
12053 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
12054 #define RTC_ALRMBR_PM_Pos (22U)
12055 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
12056 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
12057 #define RTC_ALRMBR_HT_Pos (20U)
12058 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
12059 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
12060 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
12061 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
12062 #define RTC_ALRMBR_HU_Pos (16U)
12063 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
12064 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
12065 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
12066 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
12067 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
12068 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
12069 #define RTC_ALRMBR_MSK2_Pos (15U)
12070 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
12071 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12072 #define RTC_ALRMBR_MNT_Pos (12U)
12073 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
12074 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12075 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
12076 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
12077 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
12078 #define RTC_ALRMBR_MNU_Pos (8U)
12079 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
12080 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12081 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
12082 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
12083 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
12084 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
12085 #define RTC_ALRMBR_MSK1_Pos (7U)
12086 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
12087 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12088 #define RTC_ALRMBR_ST_Pos (4U)
12089 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
12090 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12091 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
12092 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
12093 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
12094 #define RTC_ALRMBR_SU_Pos (0U)
12095 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
12096 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12097 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
12098 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
12099 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
12100 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
12102 /******************** Bits definition for RTC_WPR register ******************/
12103 #define RTC_WPR_KEY_Pos (0U)
12104 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
12105 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
12106 
12107 /******************** Bits definition for RTC_SSR register ******************/
12108 #define RTC_SSR_SS_Pos (0U)
12109 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
12110 #define RTC_SSR_SS RTC_SSR_SS_Msk
12111 
12112 /******************** Bits definition for RTC_SHIFTR register ***************/
12113 #define RTC_SHIFTR_SUBFS_Pos (0U)
12114 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
12115 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12116 #define RTC_SHIFTR_ADD1S_Pos (31U)
12117 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
12118 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12119 
12120 /******************** Bits definition for RTC_TSTR register *****************/
12121 #define RTC_TSTR_PM_Pos (22U)
12122 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
12123 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
12124 #define RTC_TSTR_HT_Pos (20U)
12125 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
12126 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
12127 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
12128 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
12129 #define RTC_TSTR_HU_Pos (16U)
12130 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
12131 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
12132 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
12133 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
12134 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
12135 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
12136 #define RTC_TSTR_MNT_Pos (12U)
12137 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
12138 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12139 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
12140 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
12141 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
12142 #define RTC_TSTR_MNU_Pos (8U)
12143 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
12144 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12145 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
12146 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
12147 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
12148 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
12149 #define RTC_TSTR_ST_Pos (4U)
12150 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
12151 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
12152 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
12153 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
12154 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
12155 #define RTC_TSTR_SU_Pos (0U)
12156 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
12157 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
12158 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
12159 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
12160 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
12161 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
12163 /******************** Bits definition for RTC_TSDR register *****************/
12164 #define RTC_TSDR_WDU_Pos (13U)
12165 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
12166 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12167 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
12168 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
12169 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
12170 #define RTC_TSDR_MT_Pos (12U)
12171 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
12172 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
12173 #define RTC_TSDR_MU_Pos (8U)
12174 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
12175 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
12176 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
12177 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
12178 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
12179 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
12180 #define RTC_TSDR_DT_Pos (4U)
12181 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
12182 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
12183 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
12184 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
12185 #define RTC_TSDR_DU_Pos (0U)
12186 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
12187 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
12188 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
12189 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
12190 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
12191 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
12193 /******************** Bits definition for RTC_TSSSR register ****************/
12194 #define RTC_TSSSR_SS_Pos (0U)
12195 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
12196 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12197 
12198 /******************** Bits definition for RTC_CAL register *****************/
12199 #define RTC_CALR_CALP_Pos (15U)
12200 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
12201 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
12202 #define RTC_CALR_CALW8_Pos (14U)
12203 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
12204 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12205 #define RTC_CALR_CALW16_Pos (13U)
12206 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
12207 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12208 #define RTC_CALR_CALM_Pos (0U)
12209 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
12210 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
12211 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
12212 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
12213 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
12214 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
12215 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
12216 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
12217 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
12218 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
12219 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
12221 /******************** Bits definition for RTC_TAMPCR register ***************/
12222 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
12223 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
12224 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
12225 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
12226 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
12227 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
12228 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
12229 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
12230 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
12231 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
12232 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
12233 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
12234 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
12235 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
12236 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
12237 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
12238 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
12239 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
12240 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
12241 #define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
12242 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
12243 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
12244 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
12245 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
12246 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
12247 #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
12248 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
12249 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
12250 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
12251 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
12252 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
12253 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
12254 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
12255 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
12256 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
12257 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
12258 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
12259 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
12260 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
12261 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
12262 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
12263 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
12264 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
12265 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
12266 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
12267 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
12268 #define RTC_TAMPCR_TAMPTS_Pos (7U)
12269 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
12270 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
12271 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
12272 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
12273 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
12274 #define RTC_TAMPCR_TAMP3E_Pos (5U)
12275 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
12276 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
12277 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
12278 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
12279 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
12280 #define RTC_TAMPCR_TAMP2E_Pos (3U)
12281 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
12282 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
12283 #define RTC_TAMPCR_TAMPIE_Pos (2U)
12284 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
12285 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
12286 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
12287 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
12288 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
12289 #define RTC_TAMPCR_TAMP1E_Pos (0U)
12290 #define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
12291 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
12292 
12293 /******************** Bits definition for RTC_ALRMASSR register *************/
12294 #define RTC_ALRMASSR_MASKSS_Pos (24U)
12295 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
12296 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12297 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
12298 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
12299 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
12300 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
12301 #define RTC_ALRMASSR_SS_Pos (0U)
12302 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
12303 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12304 
12305 /******************** Bits definition for RTC_ALRMBSSR register *************/
12306 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
12307 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
12308 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12309 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
12310 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
12311 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
12312 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
12313 #define RTC_ALRMBSSR_SS_Pos (0U)
12314 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
12315 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12316 
12317 /******************** Bits definition for RTC_0R register *******************/
12318 #define RTC_OR_OUT_RMP_Pos (1U)
12319 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
12320 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
12321 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
12322 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
12323 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
12324 
12325 
12326 /******************** Bits definition for RTC_BKP0R register ****************/
12327 #define RTC_BKP0R_Pos (0U)
12328 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
12329 #define RTC_BKP0R RTC_BKP0R_Msk
12330 
12331 /******************** Bits definition for RTC_BKP1R register ****************/
12332 #define RTC_BKP1R_Pos (0U)
12333 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
12334 #define RTC_BKP1R RTC_BKP1R_Msk
12335 
12336 /******************** Bits definition for RTC_BKP2R register ****************/
12337 #define RTC_BKP2R_Pos (0U)
12338 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
12339 #define RTC_BKP2R RTC_BKP2R_Msk
12340 
12341 /******************** Bits definition for RTC_BKP3R register ****************/
12342 #define RTC_BKP3R_Pos (0U)
12343 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
12344 #define RTC_BKP3R RTC_BKP3R_Msk
12345 
12346 /******************** Bits definition for RTC_BKP4R register ****************/
12347 #define RTC_BKP4R_Pos (0U)
12348 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
12349 #define RTC_BKP4R RTC_BKP4R_Msk
12350 
12351 /******************** Bits definition for RTC_BKP5R register ****************/
12352 #define RTC_BKP5R_Pos (0U)
12353 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
12354 #define RTC_BKP5R RTC_BKP5R_Msk
12355 
12356 /******************** Bits definition for RTC_BKP6R register ****************/
12357 #define RTC_BKP6R_Pos (0U)
12358 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
12359 #define RTC_BKP6R RTC_BKP6R_Msk
12360 
12361 /******************** Bits definition for RTC_BKP7R register ****************/
12362 #define RTC_BKP7R_Pos (0U)
12363 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
12364 #define RTC_BKP7R RTC_BKP7R_Msk
12365 
12366 /******************** Bits definition for RTC_BKP8R register ****************/
12367 #define RTC_BKP8R_Pos (0U)
12368 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
12369 #define RTC_BKP8R RTC_BKP8R_Msk
12370 
12371 /******************** Bits definition for RTC_BKP9R register ****************/
12372 #define RTC_BKP9R_Pos (0U)
12373 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
12374 #define RTC_BKP9R RTC_BKP9R_Msk
12375 
12376 /******************** Bits definition for RTC_BKP10R register ***************/
12377 #define RTC_BKP10R_Pos (0U)
12378 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
12379 #define RTC_BKP10R RTC_BKP10R_Msk
12380 
12381 /******************** Bits definition for RTC_BKP11R register ***************/
12382 #define RTC_BKP11R_Pos (0U)
12383 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
12384 #define RTC_BKP11R RTC_BKP11R_Msk
12385 
12386 /******************** Bits definition for RTC_BKP12R register ***************/
12387 #define RTC_BKP12R_Pos (0U)
12388 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
12389 #define RTC_BKP12R RTC_BKP12R_Msk
12390 
12391 /******************** Bits definition for RTC_BKP13R register ***************/
12392 #define RTC_BKP13R_Pos (0U)
12393 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
12394 #define RTC_BKP13R RTC_BKP13R_Msk
12395 
12396 /******************** Bits definition for RTC_BKP14R register ***************/
12397 #define RTC_BKP14R_Pos (0U)
12398 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
12399 #define RTC_BKP14R RTC_BKP14R_Msk
12400 
12401 /******************** Bits definition for RTC_BKP15R register ***************/
12402 #define RTC_BKP15R_Pos (0U)
12403 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
12404 #define RTC_BKP15R RTC_BKP15R_Msk
12405 
12406 /******************** Bits definition for RTC_BKP16R register ***************/
12407 #define RTC_BKP16R_Pos (0U)
12408 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
12409 #define RTC_BKP16R RTC_BKP16R_Msk
12410 
12411 /******************** Bits definition for RTC_BKP17R register ***************/
12412 #define RTC_BKP17R_Pos (0U)
12413 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
12414 #define RTC_BKP17R RTC_BKP17R_Msk
12415 
12416 /******************** Bits definition for RTC_BKP18R register ***************/
12417 #define RTC_BKP18R_Pos (0U)
12418 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
12419 #define RTC_BKP18R RTC_BKP18R_Msk
12420 
12421 /******************** Bits definition for RTC_BKP19R register ***************/
12422 #define RTC_BKP19R_Pos (0U)
12423 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
12424 #define RTC_BKP19R RTC_BKP19R_Msk
12425 
12426 /******************** Bits definition for RTC_BKP20R register ***************/
12427 #define RTC_BKP20R_Pos (0U)
12428 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
12429 #define RTC_BKP20R RTC_BKP20R_Msk
12430 
12431 /******************** Bits definition for RTC_BKP21R register ***************/
12432 #define RTC_BKP21R_Pos (0U)
12433 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
12434 #define RTC_BKP21R RTC_BKP21R_Msk
12435 
12436 /******************** Bits definition for RTC_BKP22R register ***************/
12437 #define RTC_BKP22R_Pos (0U)
12438 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
12439 #define RTC_BKP22R RTC_BKP22R_Msk
12440 
12441 /******************** Bits definition for RTC_BKP23R register ***************/
12442 #define RTC_BKP23R_Pos (0U)
12443 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
12444 #define RTC_BKP23R RTC_BKP23R_Msk
12445 
12446 /******************** Bits definition for RTC_BKP24R register ***************/
12447 #define RTC_BKP24R_Pos (0U)
12448 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
12449 #define RTC_BKP24R RTC_BKP24R_Msk
12450 
12451 /******************** Bits definition for RTC_BKP25R register ***************/
12452 #define RTC_BKP25R_Pos (0U)
12453 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
12454 #define RTC_BKP25R RTC_BKP25R_Msk
12455 
12456 /******************** Bits definition for RTC_BKP26R register ***************/
12457 #define RTC_BKP26R_Pos (0U)
12458 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
12459 #define RTC_BKP26R RTC_BKP26R_Msk
12460 
12461 /******************** Bits definition for RTC_BKP27R register ***************/
12462 #define RTC_BKP27R_Pos (0U)
12463 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
12464 #define RTC_BKP27R RTC_BKP27R_Msk
12465 
12466 /******************** Bits definition for RTC_BKP28R register ***************/
12467 #define RTC_BKP28R_Pos (0U)
12468 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
12469 #define RTC_BKP28R RTC_BKP28R_Msk
12470 
12471 /******************** Bits definition for RTC_BKP29R register ***************/
12472 #define RTC_BKP29R_Pos (0U)
12473 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
12474 #define RTC_BKP29R RTC_BKP29R_Msk
12475 
12476 /******************** Bits definition for RTC_BKP30R register ***************/
12477 #define RTC_BKP30R_Pos (0U)
12478 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
12479 #define RTC_BKP30R RTC_BKP30R_Msk
12480 
12481 /******************** Bits definition for RTC_BKP31R register ***************/
12482 #define RTC_BKP31R_Pos (0U)
12483 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
12484 #define RTC_BKP31R RTC_BKP31R_Msk
12485 
12486 /******************** Number of backup registers ******************************/
12487 #define RTC_BKP_NUMBER 32U
12488 
12489 /******************************************************************************/
12490 /* */
12491 /* Serial Audio Interface */
12492 /* */
12493 /******************************************************************************/
12494 /******************** Bit definition for SAI_GCR register *******************/
12495 #define SAI_GCR_SYNCIN_Pos (0U)
12496 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
12497 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
12498 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
12499 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
12501 #define SAI_GCR_SYNCOUT_Pos (4U)
12502 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
12503 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
12504 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
12505 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
12507 /******************* Bit definition for SAI_xCR1 register *******************/
12508 #define SAI_xCR1_MODE_Pos (0U)
12509 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
12510 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
12511 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
12512 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
12514 #define SAI_xCR1_PRTCFG_Pos (2U)
12515 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
12516 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
12517 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
12518 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
12520 #define SAI_xCR1_DS_Pos (5U)
12521 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
12522 #define SAI_xCR1_DS SAI_xCR1_DS_Msk
12523 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
12524 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
12525 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
12527 #define SAI_xCR1_LSBFIRST_Pos (8U)
12528 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
12529 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
12530 #define SAI_xCR1_CKSTR_Pos (9U)
12531 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
12532 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
12534 #define SAI_xCR1_SYNCEN_Pos (10U)
12535 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
12536 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
12537 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
12538 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
12540 #define SAI_xCR1_MONO_Pos (12U)
12541 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
12542 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
12543 #define SAI_xCR1_OUTDRIV_Pos (13U)
12544 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
12545 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
12546 #define SAI_xCR1_SAIEN_Pos (16U)
12547 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
12548 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
12549 #define SAI_xCR1_DMAEN_Pos (17U)
12550 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
12551 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
12552 #define SAI_xCR1_NODIV_Pos (19U)
12553 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
12554 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
12556 #define SAI_xCR1_MCKDIV_Pos (20U)
12557 #define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
12558 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
12559 #define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
12560 #define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
12561 #define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
12562 #define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
12564 /******************* Bit definition for SAI_xCR2 register *******************/
12565 #define SAI_xCR2_FTH_Pos (0U)
12566 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
12567 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
12568 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
12569 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
12570 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
12572 #define SAI_xCR2_FFLUSH_Pos (3U)
12573 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
12574 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
12575 #define SAI_xCR2_TRIS_Pos (4U)
12576 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
12577 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
12578 #define SAI_xCR2_MUTE_Pos (5U)
12579 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
12580 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
12581 #define SAI_xCR2_MUTEVAL_Pos (6U)
12582 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
12583 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
12586 #define SAI_xCR2_MUTECNT_Pos (7U)
12587 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
12588 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
12589 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
12590 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
12591 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
12592 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
12593 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
12594 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
12596 #define SAI_xCR2_CPL_Pos (13U)
12597 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
12598 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
12599 #define SAI_xCR2_COMP_Pos (14U)
12600 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
12601 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
12602 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
12603 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
12606 /****************** Bit definition for SAI_xFRCR register *******************/
12607 #define SAI_xFRCR_FRL_Pos (0U)
12608 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
12609 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
12610 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
12611 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
12612 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
12613 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
12614 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
12615 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
12616 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
12617 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
12619 #define SAI_xFRCR_FSALL_Pos (8U)
12620 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
12621 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
12622 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
12623 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
12624 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
12625 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
12626 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
12627 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
12628 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
12630 #define SAI_xFRCR_FSDEF_Pos (16U)
12631 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
12632 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
12633 #define SAI_xFRCR_FSPOL_Pos (17U)
12634 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
12635 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
12636 #define SAI_xFRCR_FSOFF_Pos (18U)
12637 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
12638 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
12640 /****************** Bit definition for SAI_xSLOTR register *******************/
12641 #define SAI_xSLOTR_FBOFF_Pos (0U)
12642 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
12643 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
12644 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
12645 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
12646 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
12647 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
12648 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
12650 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
12651 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
12652 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
12653 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
12654 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
12656 #define SAI_xSLOTR_NBSLOT_Pos (8U)
12657 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
12658 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
12659 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
12660 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
12661 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
12662 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
12664 #define SAI_xSLOTR_SLOTEN_Pos (16U)
12665 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
12666 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
12668 /******************* Bit definition for SAI_xIMR register *******************/
12669 #define SAI_xIMR_OVRUDRIE_Pos (0U)
12670 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
12671 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
12672 #define SAI_xIMR_MUTEDETIE_Pos (1U)
12673 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
12674 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
12675 #define SAI_xIMR_WCKCFGIE_Pos (2U)
12676 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
12677 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
12678 #define SAI_xIMR_FREQIE_Pos (3U)
12679 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
12680 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
12681 #define SAI_xIMR_CNRDYIE_Pos (4U)
12682 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
12683 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
12684 #define SAI_xIMR_AFSDETIE_Pos (5U)
12685 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
12686 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
12687 #define SAI_xIMR_LFSDETIE_Pos (6U)
12688 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
12689 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
12691 /******************** Bit definition for SAI_xSR register *******************/
12692 #define SAI_xSR_OVRUDR_Pos (0U)
12693 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
12694 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
12695 #define SAI_xSR_MUTEDET_Pos (1U)
12696 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
12697 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
12698 #define SAI_xSR_WCKCFG_Pos (2U)
12699 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
12700 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
12701 #define SAI_xSR_FREQ_Pos (3U)
12702 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
12703 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
12704 #define SAI_xSR_CNRDY_Pos (4U)
12705 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
12706 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
12707 #define SAI_xSR_AFSDET_Pos (5U)
12708 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
12709 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
12710 #define SAI_xSR_LFSDET_Pos (6U)
12711 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
12712 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
12714 #define SAI_xSR_FLVL_Pos (16U)
12715 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
12716 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
12717 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
12718 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
12719 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
12721 /****************** Bit definition for SAI_xCLRFR register ******************/
12722 #define SAI_xCLRFR_COVRUDR_Pos (0U)
12723 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
12724 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
12725 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
12726 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
12727 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
12728 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
12729 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
12730 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
12731 #define SAI_xCLRFR_CFREQ_Pos (3U)
12732 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
12733 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
12734 #define SAI_xCLRFR_CCNRDY_Pos (4U)
12735 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
12736 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
12737 #define SAI_xCLRFR_CAFSDET_Pos (5U)
12738 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
12739 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
12740 #define SAI_xCLRFR_CLFSDET_Pos (6U)
12741 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
12742 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
12744 /****************** Bit definition for SAI_xDR register ******************/
12745 #define SAI_xDR_DATA_Pos (0U)
12746 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
12747 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
12748 
12749 /******************************************************************************/
12750 /* */
12751 /* LCD Controller (LCD) */
12752 /* */
12753 /******************************************************************************/
12754 
12755 /******************* Bit definition for LCD_CR register *********************/
12756 #define LCD_CR_LCDEN_Pos (0U)
12757 #define LCD_CR_LCDEN_Msk (0x1UL << LCD_CR_LCDEN_Pos)
12758 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk
12759 #define LCD_CR_VSEL_Pos (1U)
12760 #define LCD_CR_VSEL_Msk (0x1UL << LCD_CR_VSEL_Pos)
12761 #define LCD_CR_VSEL LCD_CR_VSEL_Msk
12763 #define LCD_CR_DUTY_Pos (2U)
12764 #define LCD_CR_DUTY_Msk (0x7UL << LCD_CR_DUTY_Pos)
12765 #define LCD_CR_DUTY LCD_CR_DUTY_Msk
12766 #define LCD_CR_DUTY_0 (0x1UL << LCD_CR_DUTY_Pos)
12767 #define LCD_CR_DUTY_1 (0x2UL << LCD_CR_DUTY_Pos)
12768 #define LCD_CR_DUTY_2 (0x4UL << LCD_CR_DUTY_Pos)
12770 #define LCD_CR_BIAS_Pos (5U)
12771 #define LCD_CR_BIAS_Msk (0x3UL << LCD_CR_BIAS_Pos)
12772 #define LCD_CR_BIAS LCD_CR_BIAS_Msk
12773 #define LCD_CR_BIAS_0 (0x1UL << LCD_CR_BIAS_Pos)
12774 #define LCD_CR_BIAS_1 (0x2UL << LCD_CR_BIAS_Pos)
12776 #define LCD_CR_MUX_SEG_Pos (7U)
12777 #define LCD_CR_MUX_SEG_Msk (0x1UL << LCD_CR_MUX_SEG_Pos)
12778 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk
12779 #define LCD_CR_BUFEN_Pos (8U)
12780 #define LCD_CR_BUFEN_Msk (0x1UL << LCD_CR_BUFEN_Pos)
12781 #define LCD_CR_BUFEN LCD_CR_BUFEN_Msk
12783 /******************* Bit definition for LCD_FCR register ********************/
12784 #define LCD_FCR_HD_Pos (0U)
12785 #define LCD_FCR_HD_Msk (0x1UL << LCD_FCR_HD_Pos)
12786 #define LCD_FCR_HD LCD_FCR_HD_Msk
12787 #define LCD_FCR_SOFIE_Pos (1U)
12788 #define LCD_FCR_SOFIE_Msk (0x1UL << LCD_FCR_SOFIE_Pos)
12789 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk
12790 #define LCD_FCR_UDDIE_Pos (3U)
12791 #define LCD_FCR_UDDIE_Msk (0x1UL << LCD_FCR_UDDIE_Pos)
12792 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk
12794 #define LCD_FCR_PON_Pos (4U)
12795 #define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos)
12796 #define LCD_FCR_PON LCD_FCR_PON_Msk
12797 #define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos)
12798 #define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos)
12799 #define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos)
12801 #define LCD_FCR_DEAD_Pos (7U)
12802 #define LCD_FCR_DEAD_Msk (0x7UL << LCD_FCR_DEAD_Pos)
12803 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk
12804 #define LCD_FCR_DEAD_0 (0x1UL << LCD_FCR_DEAD_Pos)
12805 #define LCD_FCR_DEAD_1 (0x2UL << LCD_FCR_DEAD_Pos)
12806 #define LCD_FCR_DEAD_2 (0x4UL << LCD_FCR_DEAD_Pos)
12808 #define LCD_FCR_CC_Pos (10U)
12809 #define LCD_FCR_CC_Msk (0x7UL << LCD_FCR_CC_Pos)
12810 #define LCD_FCR_CC LCD_FCR_CC_Msk
12811 #define LCD_FCR_CC_0 (0x1UL << LCD_FCR_CC_Pos)
12812 #define LCD_FCR_CC_1 (0x2UL << LCD_FCR_CC_Pos)
12813 #define LCD_FCR_CC_2 (0x4UL << LCD_FCR_CC_Pos)
12815 #define LCD_FCR_BLINKF_Pos (13U)
12816 #define LCD_FCR_BLINKF_Msk (0x7UL << LCD_FCR_BLINKF_Pos)
12817 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk
12818 #define LCD_FCR_BLINKF_0 (0x1UL << LCD_FCR_BLINKF_Pos)
12819 #define LCD_FCR_BLINKF_1 (0x2UL << LCD_FCR_BLINKF_Pos)
12820 #define LCD_FCR_BLINKF_2 (0x4UL << LCD_FCR_BLINKF_Pos)
12822 #define LCD_FCR_BLINK_Pos (16U)
12823 #define LCD_FCR_BLINK_Msk (0x3UL << LCD_FCR_BLINK_Pos)
12824 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk
12825 #define LCD_FCR_BLINK_0 (0x1UL << LCD_FCR_BLINK_Pos)
12826 #define LCD_FCR_BLINK_1 (0x2UL << LCD_FCR_BLINK_Pos)
12828 #define LCD_FCR_DIV_Pos (18U)
12829 #define LCD_FCR_DIV_Msk (0xFUL << LCD_FCR_DIV_Pos)
12830 #define LCD_FCR_DIV LCD_FCR_DIV_Msk
12831 #define LCD_FCR_PS_Pos (22U)
12832 #define LCD_FCR_PS_Msk (0xFUL << LCD_FCR_PS_Pos)
12833 #define LCD_FCR_PS LCD_FCR_PS_Msk
12835 /******************* Bit definition for LCD_SR register *********************/
12836 #define LCD_SR_ENS_Pos (0U)
12837 #define LCD_SR_ENS_Msk (0x1UL << LCD_SR_ENS_Pos)
12838 #define LCD_SR_ENS LCD_SR_ENS_Msk
12839 #define LCD_SR_SOF_Pos (1U)
12840 #define LCD_SR_SOF_Msk (0x1UL << LCD_SR_SOF_Pos)
12841 #define LCD_SR_SOF LCD_SR_SOF_Msk
12842 #define LCD_SR_UDR_Pos (2U)
12843 #define LCD_SR_UDR_Msk (0x1UL << LCD_SR_UDR_Pos)
12844 #define LCD_SR_UDR LCD_SR_UDR_Msk
12845 #define LCD_SR_UDD_Pos (3U)
12846 #define LCD_SR_UDD_Msk (0x1UL << LCD_SR_UDD_Pos)
12847 #define LCD_SR_UDD LCD_SR_UDD_Msk
12848 #define LCD_SR_RDY_Pos (4U)
12849 #define LCD_SR_RDY_Msk (0x1UL << LCD_SR_RDY_Pos)
12850 #define LCD_SR_RDY LCD_SR_RDY_Msk
12851 #define LCD_SR_FCRSR_Pos (5U)
12852 #define LCD_SR_FCRSR_Msk (0x1UL << LCD_SR_FCRSR_Pos)
12853 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk
12855 /******************* Bit definition for LCD_CLR register ********************/
12856 #define LCD_CLR_SOFC_Pos (1U)
12857 #define LCD_CLR_SOFC_Msk (0x1UL << LCD_CLR_SOFC_Pos)
12858 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk
12859 #define LCD_CLR_UDDC_Pos (3U)
12860 #define LCD_CLR_UDDC_Msk (0x1UL << LCD_CLR_UDDC_Pos)
12861 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk
12863 /******************* Bit definition for LCD_RAM register ********************/
12864 #define LCD_RAM_SEGMENT_DATA_Pos (0U)
12865 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)
12866 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk
12868 /******************************************************************************/
12869 /* */
12870 /* SDMMC Interface */
12871 /* */
12872 /******************************************************************************/
12873 /****************** Bit definition for SDMMC_POWER register ******************/
12874 #define SDMMC_POWER_PWRCTRL_Pos (0U)
12875 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
12876 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
12877 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
12878 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
12880 /****************** Bit definition for SDMMC_CLKCR register ******************/
12881 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
12882 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)
12883 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
12884 #define SDMMC_CLKCR_CLKEN_Pos (8U)
12885 #define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos)
12886 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk
12887 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
12888 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
12889 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
12890 #define SDMMC_CLKCR_BYPASS_Pos (10U)
12891 #define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos)
12892 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk
12894 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
12895 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
12896 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
12897 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
12898 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
12900 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
12901 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
12902 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
12903 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
12904 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
12905 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
12907 /******************* Bit definition for SDMMC_ARG register *******************/
12908 #define SDMMC_ARG_CMDARG_Pos (0U)
12909 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
12910 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
12912 /******************* Bit definition for SDMMC_CMD register *******************/
12913 #define SDMMC_CMD_CMDINDEX_Pos (0U)
12914 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
12915 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
12917 #define SDMMC_CMD_WAITRESP_Pos (6U)
12918 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
12919 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
12920 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
12921 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
12923 #define SDMMC_CMD_WAITINT_Pos (8U)
12924 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
12925 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
12926 #define SDMMC_CMD_WAITPEND_Pos (9U)
12927 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
12928 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
12929 #define SDMMC_CMD_CPSMEN_Pos (10U)
12930 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
12931 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
12932 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
12933 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)
12934 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk
12936 /***************** Bit definition for SDMMC_RESPCMD register *****************/
12937 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
12938 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
12939 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
12941 /****************** Bit definition for SDMMC_RESP1 register ******************/
12942 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
12943 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
12944 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
12946 /****************** Bit definition for SDMMC_RESP2 register ******************/
12947 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
12948 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
12949 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
12951 /****************** Bit definition for SDMMC_RESP3 register ******************/
12952 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
12953 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
12954 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
12956 /****************** Bit definition for SDMMC_RESP4 register ******************/
12957 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
12958 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
12959 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
12961 /****************** Bit definition for SDMMC_DTIMER register *****************/
12962 #define SDMMC_DTIMER_DATATIME_Pos (0U)
12963 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
12964 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
12966 /****************** Bit definition for SDMMC_DLEN register *******************/
12967 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
12968 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
12969 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
12971 /****************** Bit definition for SDMMC_DCTRL register ******************/
12972 #define SDMMC_DCTRL_DTEN_Pos (0U)
12973 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
12974 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
12975 #define SDMMC_DCTRL_DTDIR_Pos (1U)
12976 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
12977 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
12978 #define SDMMC_DCTRL_DTMODE_Pos (2U)
12979 #define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
12980 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
12981 #define SDMMC_DCTRL_DMAEN_Pos (3U)
12982 #define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos)
12983 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk
12985 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
12986 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12987 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
12988 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12989 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12990 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12991 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12993 #define SDMMC_DCTRL_RWSTART_Pos (8U)
12994 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
12995 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
12996 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
12997 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
12998 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
12999 #define SDMMC_DCTRL_RWMOD_Pos (10U)
13000 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
13001 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
13002 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
13003 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
13004 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
13006 /****************** Bit definition for SDMMC_DCOUNT register *****************/
13007 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
13008 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
13009 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
13011 /****************** Bit definition for SDMMC_STA register ********************/
13012 #define SDMMC_STA_CCRCFAIL_Pos (0U)
13013 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
13014 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
13015 #define SDMMC_STA_DCRCFAIL_Pos (1U)
13016 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
13017 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
13018 #define SDMMC_STA_CTIMEOUT_Pos (2U)
13019 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
13020 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
13021 #define SDMMC_STA_DTIMEOUT_Pos (3U)
13022 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
13023 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
13024 #define SDMMC_STA_TXUNDERR_Pos (4U)
13025 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
13026 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
13027 #define SDMMC_STA_RXOVERR_Pos (5U)
13028 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
13029 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
13030 #define SDMMC_STA_CMDREND_Pos (6U)
13031 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
13032 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
13033 #define SDMMC_STA_CMDSENT_Pos (7U)
13034 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
13035 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
13036 #define SDMMC_STA_DATAEND_Pos (8U)
13037 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
13038 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
13039 #define SDMMC_STA_STBITERR_Pos (9U)
13040 #define SDMMC_STA_STBITERR_Msk (0x1UL << SDMMC_STA_STBITERR_Pos)
13041 #define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk
13042 #define SDMMC_STA_DBCKEND_Pos (10U)
13043 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
13044 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
13045 #define SDMMC_STA_CMDACT_Pos (11U)
13046 #define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos)
13047 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk
13048 #define SDMMC_STA_TXACT_Pos (12U)
13049 #define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos)
13050 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk
13051 #define SDMMC_STA_RXACT_Pos (13U)
13052 #define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos)
13053 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk
13054 #define SDMMC_STA_TXFIFOHE_Pos (14U)
13055 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
13056 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
13057 #define SDMMC_STA_RXFIFOHF_Pos (15U)
13058 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
13059 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
13060 #define SDMMC_STA_TXFIFOF_Pos (16U)
13061 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
13062 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
13063 #define SDMMC_STA_RXFIFOF_Pos (17U)
13064 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
13065 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
13066 #define SDMMC_STA_TXFIFOE_Pos (18U)
13067 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
13068 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
13069 #define SDMMC_STA_RXFIFOE_Pos (19U)
13070 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
13071 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
13072 #define SDMMC_STA_TXDAVL_Pos (20U)
13073 #define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos)
13074 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk
13075 #define SDMMC_STA_RXDAVL_Pos (21U)
13076 #define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos)
13077 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk
13078 #define SDMMC_STA_SDIOIT_Pos (22U)
13079 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
13080 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
13082 /******************* Bit definition for SDMMC_ICR register *******************/
13083 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
13084 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
13085 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
13086 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
13087 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
13088 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
13089 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
13090 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
13091 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
13092 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
13093 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
13094 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
13095 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
13096 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
13097 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
13098 #define SDMMC_ICR_RXOVERRC_Pos (5U)
13099 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
13100 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
13101 #define SDMMC_ICR_CMDRENDC_Pos (6U)
13102 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
13103 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
13104 #define SDMMC_ICR_CMDSENTC_Pos (7U)
13105 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
13106 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
13107 #define SDMMC_ICR_DATAENDC_Pos (8U)
13108 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
13109 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
13110 #define SDMMC_ICR_STBITERRC_Pos (9U)
13111 #define SDMMC_ICR_STBITERRC_Msk (0x1UL << SDMMC_ICR_STBITERRC_Pos)
13112 #define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk
13113 #define SDMMC_ICR_DBCKENDC_Pos (10U)
13114 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
13115 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
13116 #define SDMMC_ICR_SDIOITC_Pos (22U)
13117 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
13118 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
13120 /****************** Bit definition for SDMMC_MASK register *******************/
13121 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
13122 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
13123 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
13124 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
13125 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
13126 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
13127 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
13128 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
13129 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
13130 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
13131 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
13132 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
13133 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
13134 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
13135 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
13136 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
13137 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
13138 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
13139 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
13140 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
13141 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
13142 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
13143 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
13144 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
13145 #define SDMMC_MASK_DATAENDIE_Pos (8U)
13146 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
13147 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
13148 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
13149 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
13150 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
13151 #define SDMMC_MASK_CMDACTIE_Pos (11U)
13152 #define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos)
13153 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk
13154 #define SDMMC_MASK_TXACTIE_Pos (12U)
13155 #define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos)
13156 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk
13157 #define SDMMC_MASK_RXACTIE_Pos (13U)
13158 #define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos)
13159 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk
13160 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
13161 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
13162 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
13163 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
13164 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
13165 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
13166 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
13167 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)
13168 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk
13169 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
13170 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
13171 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
13172 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
13173 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
13174 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
13175 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
13176 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)
13177 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk
13178 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
13179 #define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)
13180 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk
13181 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
13182 #define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)
13183 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk
13184 #define SDMMC_MASK_SDIOITIE_Pos (22U)
13185 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
13186 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
13188 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
13189 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
13190 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos)
13191 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk
13193 /****************** Bit definition for SDMMC_FIFO register *******************/
13194 #define SDMMC_FIFO_FIFODATA_Pos (0U)
13195 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
13196 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
13198 /******************************************************************************/
13199 /* */
13200 /* Serial Peripheral Interface (SPI) */
13201 /* */
13202 /******************************************************************************/
13203 /******************* Bit definition for SPI_CR1 register ********************/
13204 #define SPI_CR1_CPHA_Pos (0U)
13205 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
13206 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
13207 #define SPI_CR1_CPOL_Pos (1U)
13208 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
13209 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
13210 #define SPI_CR1_MSTR_Pos (2U)
13211 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
13212 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
13214 #define SPI_CR1_BR_Pos (3U)
13215 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
13216 #define SPI_CR1_BR SPI_CR1_BR_Msk
13217 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
13218 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
13219 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
13221 #define SPI_CR1_SPE_Pos (6U)
13222 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
13223 #define SPI_CR1_SPE SPI_CR1_SPE_Msk
13224 #define SPI_CR1_LSBFIRST_Pos (7U)
13225 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
13226 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
13227 #define SPI_CR1_SSI_Pos (8U)
13228 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
13229 #define SPI_CR1_SSI SPI_CR1_SSI_Msk
13230 #define SPI_CR1_SSM_Pos (9U)
13231 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
13232 #define SPI_CR1_SSM SPI_CR1_SSM_Msk
13233 #define SPI_CR1_RXONLY_Pos (10U)
13234 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
13235 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
13236 #define SPI_CR1_CRCL_Pos (11U)
13237 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
13238 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
13239 #define SPI_CR1_CRCNEXT_Pos (12U)
13240 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
13241 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
13242 #define SPI_CR1_CRCEN_Pos (13U)
13243 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
13244 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
13245 #define SPI_CR1_BIDIOE_Pos (14U)
13246 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
13247 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
13248 #define SPI_CR1_BIDIMODE_Pos (15U)
13249 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
13250 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
13252 /******************* Bit definition for SPI_CR2 register ********************/
13253 #define SPI_CR2_RXDMAEN_Pos (0U)
13254 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
13255 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
13256 #define SPI_CR2_TXDMAEN_Pos (1U)
13257 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
13258 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
13259 #define SPI_CR2_SSOE_Pos (2U)
13260 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
13261 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
13262 #define SPI_CR2_NSSP_Pos (3U)
13263 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
13264 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
13265 #define SPI_CR2_FRF_Pos (4U)
13266 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
13267 #define SPI_CR2_FRF SPI_CR2_FRF_Msk
13268 #define SPI_CR2_ERRIE_Pos (5U)
13269 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
13270 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
13271 #define SPI_CR2_RXNEIE_Pos (6U)
13272 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
13273 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
13274 #define SPI_CR2_TXEIE_Pos (7U)
13275 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
13276 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
13277 #define SPI_CR2_DS_Pos (8U)
13278 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
13279 #define SPI_CR2_DS SPI_CR2_DS_Msk
13280 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
13281 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
13282 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
13283 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
13284 #define SPI_CR2_FRXTH_Pos (12U)
13285 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
13286 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
13287 #define SPI_CR2_LDMARX_Pos (13U)
13288 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
13289 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
13290 #define SPI_CR2_LDMATX_Pos (14U)
13291 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
13292 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
13294 /******************** Bit definition for SPI_SR register ********************/
13295 #define SPI_SR_RXNE_Pos (0U)
13296 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
13297 #define SPI_SR_RXNE SPI_SR_RXNE_Msk
13298 #define SPI_SR_TXE_Pos (1U)
13299 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
13300 #define SPI_SR_TXE SPI_SR_TXE_Msk
13301 #define SPI_SR_CHSIDE_Pos (2U)
13302 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
13303 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
13304 #define SPI_SR_UDR_Pos (3U)
13305 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
13306 #define SPI_SR_UDR SPI_SR_UDR_Msk
13307 #define SPI_SR_CRCERR_Pos (4U)
13308 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
13309 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
13310 #define SPI_SR_MODF_Pos (5U)
13311 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
13312 #define SPI_SR_MODF SPI_SR_MODF_Msk
13313 #define SPI_SR_OVR_Pos (6U)
13314 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
13315 #define SPI_SR_OVR SPI_SR_OVR_Msk
13316 #define SPI_SR_BSY_Pos (7U)
13317 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
13318 #define SPI_SR_BSY SPI_SR_BSY_Msk
13319 #define SPI_SR_FRE_Pos (8U)
13320 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
13321 #define SPI_SR_FRE SPI_SR_FRE_Msk
13322 #define SPI_SR_FRLVL_Pos (9U)
13323 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
13324 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
13325 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
13326 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
13327 #define SPI_SR_FTLVL_Pos (11U)
13328 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
13329 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
13330 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
13331 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
13333 /******************** Bit definition for SPI_DR register ********************/
13334 #define SPI_DR_DR_Pos (0U)
13335 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
13336 #define SPI_DR_DR SPI_DR_DR_Msk
13338 /******************* Bit definition for SPI_CRCPR register ******************/
13339 #define SPI_CRCPR_CRCPOLY_Pos (0U)
13340 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
13341 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
13343 /****************** Bit definition for SPI_RXCRCR register ******************/
13344 #define SPI_RXCRCR_RXCRC_Pos (0U)
13345 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
13346 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
13348 /****************** Bit definition for SPI_TXCRCR register ******************/
13349 #define SPI_TXCRCR_TXCRC_Pos (0U)
13350 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
13351 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
13353 /******************************************************************************/
13354 /* */
13355 /* QUADSPI */
13356 /* */
13357 /******************************************************************************/
13358 /***************** Bit definition for QUADSPI_CR register *******************/
13359 #define QUADSPI_CR_EN_Pos (0U)
13360 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
13361 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
13362 #define QUADSPI_CR_ABORT_Pos (1U)
13363 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
13364 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
13365 #define QUADSPI_CR_DMAEN_Pos (2U)
13366 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
13367 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
13368 #define QUADSPI_CR_TCEN_Pos (3U)
13369 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
13370 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
13371 #define QUADSPI_CR_SSHIFT_Pos (4U)
13372 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
13373 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
13374 #define QUADSPI_CR_FTHRES_Pos (8U)
13375 #define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos)
13376 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
13377 #define QUADSPI_CR_TEIE_Pos (16U)
13378 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
13379 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
13380 #define QUADSPI_CR_TCIE_Pos (17U)
13381 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
13382 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
13383 #define QUADSPI_CR_FTIE_Pos (18U)
13384 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
13385 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
13386 #define QUADSPI_CR_SMIE_Pos (19U)
13387 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
13388 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
13389 #define QUADSPI_CR_TOIE_Pos (20U)
13390 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
13391 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
13392 #define QUADSPI_CR_APMS_Pos (22U)
13393 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
13394 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
13395 #define QUADSPI_CR_PMM_Pos (23U)
13396 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
13397 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
13398 #define QUADSPI_CR_PRESCALER_Pos (24U)
13399 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
13400 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
13402 /***************** Bit definition for QUADSPI_DCR register ******************/
13403 #define QUADSPI_DCR_CKMODE_Pos (0U)
13404 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
13405 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
13406 #define QUADSPI_DCR_CSHT_Pos (8U)
13407 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
13408 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
13409 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
13410 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
13411 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
13412 #define QUADSPI_DCR_FSIZE_Pos (16U)
13413 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
13414 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
13416 /****************** Bit definition for QUADSPI_SR register *******************/
13417 #define QUADSPI_SR_TEF_Pos (0U)
13418 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
13419 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
13420 #define QUADSPI_SR_TCF_Pos (1U)
13421 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
13422 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
13423 #define QUADSPI_SR_FTF_Pos (2U)
13424 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
13425 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
13426 #define QUADSPI_SR_SMF_Pos (3U)
13427 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
13428 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
13429 #define QUADSPI_SR_TOF_Pos (4U)
13430 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
13431 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
13432 #define QUADSPI_SR_BUSY_Pos (5U)
13433 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
13434 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
13435 #define QUADSPI_SR_FLEVEL_Pos (8U)
13436 #define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos)
13437 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
13439 /****************** Bit definition for QUADSPI_FCR register ******************/
13440 #define QUADSPI_FCR_CTEF_Pos (0U)
13441 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
13442 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
13443 #define QUADSPI_FCR_CTCF_Pos (1U)
13444 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
13445 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
13446 #define QUADSPI_FCR_CSMF_Pos (3U)
13447 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
13448 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
13449 #define QUADSPI_FCR_CTOF_Pos (4U)
13450 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
13451 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
13453 /****************** Bit definition for QUADSPI_DLR register ******************/
13454 #define QUADSPI_DLR_DL_Pos (0U)
13455 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
13456 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
13458 /****************** Bit definition for QUADSPI_CCR register ******************/
13459 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13460 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
13461 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
13462 #define QUADSPI_CCR_IMODE_Pos (8U)
13463 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
13464 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
13465 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
13466 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
13467 #define QUADSPI_CCR_ADMODE_Pos (10U)
13468 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
13469 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
13470 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
13471 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
13472 #define QUADSPI_CCR_ADSIZE_Pos (12U)
13473 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
13474 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
13475 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
13476 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
13477 #define QUADSPI_CCR_ABMODE_Pos (14U)
13478 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
13479 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
13480 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
13481 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
13482 #define QUADSPI_CCR_ABSIZE_Pos (16U)
13483 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
13484 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
13485 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
13486 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
13487 #define QUADSPI_CCR_DCYC_Pos (18U)
13488 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
13489 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
13490 #define QUADSPI_CCR_DMODE_Pos (24U)
13491 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
13492 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
13493 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
13494 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
13495 #define QUADSPI_CCR_FMODE_Pos (26U)
13496 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
13497 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
13498 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
13499 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
13500 #define QUADSPI_CCR_SIOO_Pos (28U)
13501 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
13502 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
13503 #define QUADSPI_CCR_DDRM_Pos (31U)
13504 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
13505 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
13507 /****************** Bit definition for QUADSPI_AR register *******************/
13508 #define QUADSPI_AR_ADDRESS_Pos (0U)
13509 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
13510 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
13512 /****************** Bit definition for QUADSPI_ABR register ******************/
13513 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
13514 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
13515 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
13517 /****************** Bit definition for QUADSPI_DR register *******************/
13518 #define QUADSPI_DR_DATA_Pos (0U)
13519 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
13520 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
13522 /****************** Bit definition for QUADSPI_PSMKR register ****************/
13523 #define QUADSPI_PSMKR_MASK_Pos (0U)
13524 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
13525 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
13527 /****************** Bit definition for QUADSPI_PSMAR register ****************/
13528 #define QUADSPI_PSMAR_MATCH_Pos (0U)
13529 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
13530 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
13532 /****************** Bit definition for QUADSPI_PIR register *****************/
13533 #define QUADSPI_PIR_INTERVAL_Pos (0U)
13534 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
13535 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
13537 /****************** Bit definition for QUADSPI_LPTR register *****************/
13538 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13539 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
13540 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
13542 /******************************************************************************/
13543 /* */
13544 /* SYSCFG */
13545 /* */
13546 /******************************************************************************/
13547 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
13548 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
13549 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13550 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
13551 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13552 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13553 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13555 #define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
13556 #define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)
13557 #define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk
13559 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
13560 #define SYSCFG_CFGR1_FWDIS_Pos (0U)
13561 #define SYSCFG_CFGR1_FWDIS_Msk (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)
13562 #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk
13563 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
13564 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)
13565 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk
13566 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
13567 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)
13568 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk
13569 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
13570 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)
13571 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk
13572 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
13573 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)
13574 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk
13575 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
13576 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)
13577 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk
13578 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
13579 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)
13580 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk
13581 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
13582 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)
13583 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk
13584 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
13585 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)
13586 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk
13587 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000UL)
13588 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000UL)
13589 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000UL)
13590 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000UL)
13591 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000UL)
13592 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000UL)
13594 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13595 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13596 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)
13597 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
13598 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13599 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)
13600 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
13601 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13602 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)
13603 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
13604 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13605 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)
13606 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
13611 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000UL)
13612 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001UL)
13613 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002UL)
13614 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003UL)
13615 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004UL)
13616 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005UL)
13617 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006UL)
13618 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007UL)
13623 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000UL)
13624 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010UL)
13625 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020UL)
13626 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030UL)
13627 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040UL)
13628 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050UL)
13629 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060UL)
13630 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070UL)
13635 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000UL)
13636 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100UL)
13637 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200UL)
13638 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300UL)
13639 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400UL)
13640 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500UL)
13641 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600UL)
13646 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000UL)
13647 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000UL)
13648 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000UL)
13649 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000UL)
13650 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000UL)
13651 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000UL)
13652 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000UL)
13654 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13655 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13656 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)
13657 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
13658 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13659 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)
13660 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
13661 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13662 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)
13663 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
13664 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13665 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)
13666 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
13670 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000UL)
13671 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001UL)
13672 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002UL)
13673 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003UL)
13674 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004UL)
13675 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005UL)
13676 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006UL)
13681 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000UL)
13682 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010UL)
13683 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020UL)
13684 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030UL)
13685 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040UL)
13686 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050UL)
13687 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060UL)
13692 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000UL)
13693 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100UL)
13694 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200UL)
13695 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300UL)
13696 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400UL)
13697 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500UL)
13698 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600UL)
13703 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000UL)
13704 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000UL)
13705 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000UL)
13706 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000UL)
13707 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000UL)
13708 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000UL)
13709 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000UL)
13711 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13712 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13713 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)
13714 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
13715 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13716 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)
13717 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
13718 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13719 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)
13720 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
13721 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13722 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)
13723 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
13728 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000UL)
13729 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001UL)
13730 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002UL)
13731 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003UL)
13732 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004UL)
13733 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005UL)
13734 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006UL)
13739 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000UL)
13740 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010UL)
13741 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020UL)
13742 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030UL)
13743 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040UL)
13744 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050UL)
13745 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060UL)
13750 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000UL)
13751 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100UL)
13752 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200UL)
13753 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300UL)
13754 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400UL)
13755 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500UL)
13756 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000600UL)
13761 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000UL)
13762 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000UL)
13763 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000UL)
13764 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000UL)
13765 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000UL)
13766 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000UL)
13767 #define SYSCFG_EXTICR3_EXTI11_PG (0x00006000UL)
13769 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13770 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13771 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)
13772 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
13773 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13774 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)
13775 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
13776 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13777 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)
13778 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
13779 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13780 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)
13781 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
13786 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000UL)
13787 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001UL)
13788 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002UL)
13789 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003UL)
13790 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004UL)
13791 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005UL)
13792 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000006UL)
13797 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000UL)
13798 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010UL)
13799 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020UL)
13800 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030UL)
13801 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040UL)
13802 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050UL)
13803 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000060UL)
13808 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000UL)
13809 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100UL)
13810 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200UL)
13811 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300UL)
13812 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400UL)
13813 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500UL)
13814 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000600UL)
13819 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000UL)
13820 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000UL)
13821 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000UL)
13822 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000UL)
13823 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000UL)
13824 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000UL)
13825 #define SYSCFG_EXTICR4_EXTI15_PG (0x00006000UL)
13827 /****************** Bit definition for SYSCFG_SCSR register ****************/
13828 #define SYSCFG_SCSR_SRAM2ER_Pos (0U)
13829 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)
13830 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk
13831 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
13832 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)
13833 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk
13835 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
13836 #define SYSCFG_CFGR2_CLL_Pos (0U)
13837 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)
13838 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk
13839 #define SYSCFG_CFGR2_SPL_Pos (1U)
13840 #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)
13841 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk
13842 #define SYSCFG_CFGR2_PVDL_Pos (2U)
13843 #define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos)
13844 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk
13845 #define SYSCFG_CFGR2_ECCL_Pos (3U)
13846 #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)
13847 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk
13848 #define SYSCFG_CFGR2_SPF_Pos (8U)
13849 #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)
13850 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk
13852 /****************** Bit definition for SYSCFG_SWPR register ****************/
13853 #define SYSCFG_SWPR_PAGE0_Pos (0U)
13854 #define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos)
13855 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk
13856 #define SYSCFG_SWPR_PAGE1_Pos (1U)
13857 #define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos)
13858 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk
13859 #define SYSCFG_SWPR_PAGE2_Pos (2U)
13860 #define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos)
13861 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk
13862 #define SYSCFG_SWPR_PAGE3_Pos (3U)
13863 #define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos)
13864 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk
13865 #define SYSCFG_SWPR_PAGE4_Pos (4U)
13866 #define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos)
13867 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk
13868 #define SYSCFG_SWPR_PAGE5_Pos (5U)
13869 #define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos)
13870 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk
13871 #define SYSCFG_SWPR_PAGE6_Pos (6U)
13872 #define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos)
13873 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk
13874 #define SYSCFG_SWPR_PAGE7_Pos (7U)
13875 #define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos)
13876 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk
13877 #define SYSCFG_SWPR_PAGE8_Pos (8U)
13878 #define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos)
13879 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk
13880 #define SYSCFG_SWPR_PAGE9_Pos (9U)
13881 #define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos)
13882 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk
13883 #define SYSCFG_SWPR_PAGE10_Pos (10U)
13884 #define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos)
13885 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk
13886 #define SYSCFG_SWPR_PAGE11_Pos (11U)
13887 #define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos)
13888 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk
13889 #define SYSCFG_SWPR_PAGE12_Pos (12U)
13890 #define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos)
13891 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk
13892 #define SYSCFG_SWPR_PAGE13_Pos (13U)
13893 #define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos)
13894 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk
13895 #define SYSCFG_SWPR_PAGE14_Pos (14U)
13896 #define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos)
13897 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk
13898 #define SYSCFG_SWPR_PAGE15_Pos (15U)
13899 #define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos)
13900 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk
13901 #define SYSCFG_SWPR_PAGE16_Pos (16U)
13902 #define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos)
13903 #define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk
13904 #define SYSCFG_SWPR_PAGE17_Pos (17U)
13905 #define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos)
13906 #define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk
13907 #define SYSCFG_SWPR_PAGE18_Pos (18U)
13908 #define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos)
13909 #define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk
13910 #define SYSCFG_SWPR_PAGE19_Pos (19U)
13911 #define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos)
13912 #define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk
13913 #define SYSCFG_SWPR_PAGE20_Pos (20U)
13914 #define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos)
13915 #define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk
13916 #define SYSCFG_SWPR_PAGE21_Pos (21U)
13917 #define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos)
13918 #define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk
13919 #define SYSCFG_SWPR_PAGE22_Pos (22U)
13920 #define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos)
13921 #define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk
13922 #define SYSCFG_SWPR_PAGE23_Pos (23U)
13923 #define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos)
13924 #define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk
13925 #define SYSCFG_SWPR_PAGE24_Pos (24U)
13926 #define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos)
13927 #define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk
13928 #define SYSCFG_SWPR_PAGE25_Pos (25U)
13929 #define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos)
13930 #define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk
13931 #define SYSCFG_SWPR_PAGE26_Pos (26U)
13932 #define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos)
13933 #define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk
13934 #define SYSCFG_SWPR_PAGE27_Pos (27U)
13935 #define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos)
13936 #define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk
13937 #define SYSCFG_SWPR_PAGE28_Pos (28U)
13938 #define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos)
13939 #define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk
13940 #define SYSCFG_SWPR_PAGE29_Pos (29U)
13941 #define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos)
13942 #define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk
13943 #define SYSCFG_SWPR_PAGE30_Pos (30U)
13944 #define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos)
13945 #define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk
13946 #define SYSCFG_SWPR_PAGE31_Pos (31U)
13947 #define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos)
13948 #define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk
13950 /****************** Bit definition for SYSCFG_SKR register ****************/
13951 #define SYSCFG_SKR_KEY_Pos (0U)
13952 #define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos)
13953 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk
13958 /******************************************************************************/
13959 /* */
13960 /* TIM */
13961 /* */
13962 /******************************************************************************/
13963 /******************* Bit definition for TIM_CR1 register ********************/
13964 #define TIM_CR1_CEN_Pos (0U)
13965 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
13966 #define TIM_CR1_CEN TIM_CR1_CEN_Msk
13967 #define TIM_CR1_UDIS_Pos (1U)
13968 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
13969 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
13970 #define TIM_CR1_URS_Pos (2U)
13971 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
13972 #define TIM_CR1_URS TIM_CR1_URS_Msk
13973 #define TIM_CR1_OPM_Pos (3U)
13974 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
13975 #define TIM_CR1_OPM TIM_CR1_OPM_Msk
13976 #define TIM_CR1_DIR_Pos (4U)
13977 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
13978 #define TIM_CR1_DIR TIM_CR1_DIR_Msk
13980 #define TIM_CR1_CMS_Pos (5U)
13981 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
13982 #define TIM_CR1_CMS TIM_CR1_CMS_Msk
13983 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
13984 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
13986 #define TIM_CR1_ARPE_Pos (7U)
13987 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
13988 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
13990 #define TIM_CR1_CKD_Pos (8U)
13991 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
13992 #define TIM_CR1_CKD TIM_CR1_CKD_Msk
13993 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
13994 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
13996 #define TIM_CR1_UIFREMAP_Pos (11U)
13997 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
13998 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
14000 /******************* Bit definition for TIM_CR2 register ********************/
14001 #define TIM_CR2_CCPC_Pos (0U)
14002 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
14003 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
14004 #define TIM_CR2_CCUS_Pos (2U)
14005 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
14006 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
14007 #define TIM_CR2_CCDS_Pos (3U)
14008 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
14009 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
14011 #define TIM_CR2_MMS_Pos (4U)
14012 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
14013 #define TIM_CR2_MMS TIM_CR2_MMS_Msk
14014 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
14015 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
14016 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
14018 #define TIM_CR2_TI1S_Pos (7U)
14019 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
14020 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
14021 #define TIM_CR2_OIS1_Pos (8U)
14022 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
14023 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
14024 #define TIM_CR2_OIS1N_Pos (9U)
14025 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
14026 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
14027 #define TIM_CR2_OIS2_Pos (10U)
14028 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
14029 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
14030 #define TIM_CR2_OIS2N_Pos (11U)
14031 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
14032 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
14033 #define TIM_CR2_OIS3_Pos (12U)
14034 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
14035 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
14036 #define TIM_CR2_OIS3N_Pos (13U)
14037 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
14038 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
14039 #define TIM_CR2_OIS4_Pos (14U)
14040 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
14041 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
14042 #define TIM_CR2_OIS5_Pos (16U)
14043 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
14044 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
14045 #define TIM_CR2_OIS6_Pos (18U)
14046 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
14047 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
14049 #define TIM_CR2_MMS2_Pos (20U)
14050 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
14051 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
14052 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
14053 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
14054 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
14055 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
14057 /******************* Bit definition for TIM_SMCR register *******************/
14058 #define TIM_SMCR_SMS_Pos (0U)
14059 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
14060 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
14061 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
14062 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
14063 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
14064 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
14066 #define TIM_SMCR_OCCS_Pos (3U)
14067 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)
14068 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk
14070 #define TIM_SMCR_TS_Pos (4U)
14071 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
14072 #define TIM_SMCR_TS TIM_SMCR_TS_Msk
14073 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
14074 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
14075 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
14077 #define TIM_SMCR_MSM_Pos (7U)
14078 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
14079 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
14081 #define TIM_SMCR_ETF_Pos (8U)
14082 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
14083 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
14084 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
14085 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
14086 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
14087 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
14089 #define TIM_SMCR_ETPS_Pos (12U)
14090 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
14091 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
14092 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
14093 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
14095 #define TIM_SMCR_ECE_Pos (14U)
14096 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
14097 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
14098 #define TIM_SMCR_ETP_Pos (15U)
14099 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
14100 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
14102 /******************* Bit definition for TIM_DIER register *******************/
14103 #define TIM_DIER_UIE_Pos (0U)
14104 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
14105 #define TIM_DIER_UIE TIM_DIER_UIE_Msk
14106 #define TIM_DIER_CC1IE_Pos (1U)
14107 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
14108 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
14109 #define TIM_DIER_CC2IE_Pos (2U)
14110 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
14111 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
14112 #define TIM_DIER_CC3IE_Pos (3U)
14113 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
14114 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
14115 #define TIM_DIER_CC4IE_Pos (4U)
14116 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
14117 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
14118 #define TIM_DIER_COMIE_Pos (5U)
14119 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
14120 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
14121 #define TIM_DIER_TIE_Pos (6U)
14122 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
14123 #define TIM_DIER_TIE TIM_DIER_TIE_Msk
14124 #define TIM_DIER_BIE_Pos (7U)
14125 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
14126 #define TIM_DIER_BIE TIM_DIER_BIE_Msk
14127 #define TIM_DIER_UDE_Pos (8U)
14128 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
14129 #define TIM_DIER_UDE TIM_DIER_UDE_Msk
14130 #define TIM_DIER_CC1DE_Pos (9U)
14131 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
14132 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
14133 #define TIM_DIER_CC2DE_Pos (10U)
14134 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
14135 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
14136 #define TIM_DIER_CC3DE_Pos (11U)
14137 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
14138 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
14139 #define TIM_DIER_CC4DE_Pos (12U)
14140 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
14141 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
14142 #define TIM_DIER_COMDE_Pos (13U)
14143 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
14144 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
14145 #define TIM_DIER_TDE_Pos (14U)
14146 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
14147 #define TIM_DIER_TDE TIM_DIER_TDE_Msk
14149 /******************** Bit definition for TIM_SR register ********************/
14150 #define TIM_SR_UIF_Pos (0U)
14151 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
14152 #define TIM_SR_UIF TIM_SR_UIF_Msk
14153 #define TIM_SR_CC1IF_Pos (1U)
14154 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
14155 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
14156 #define TIM_SR_CC2IF_Pos (2U)
14157 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
14158 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
14159 #define TIM_SR_CC3IF_Pos (3U)
14160 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
14161 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
14162 #define TIM_SR_CC4IF_Pos (4U)
14163 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
14164 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
14165 #define TIM_SR_COMIF_Pos (5U)
14166 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
14167 #define TIM_SR_COMIF TIM_SR_COMIF_Msk
14168 #define TIM_SR_TIF_Pos (6U)
14169 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
14170 #define TIM_SR_TIF TIM_SR_TIF_Msk
14171 #define TIM_SR_BIF_Pos (7U)
14172 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
14173 #define TIM_SR_BIF TIM_SR_BIF_Msk
14174 #define TIM_SR_B2IF_Pos (8U)
14175 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
14176 #define TIM_SR_B2IF TIM_SR_B2IF_Msk
14177 #define TIM_SR_CC1OF_Pos (9U)
14178 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
14179 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
14180 #define TIM_SR_CC2OF_Pos (10U)
14181 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
14182 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
14183 #define TIM_SR_CC3OF_Pos (11U)
14184 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
14185 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
14186 #define TIM_SR_CC4OF_Pos (12U)
14187 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
14188 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
14189 #define TIM_SR_SBIF_Pos (13U)
14190 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
14191 #define TIM_SR_SBIF TIM_SR_SBIF_Msk
14192 #define TIM_SR_CC5IF_Pos (16U)
14193 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
14194 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
14195 #define TIM_SR_CC6IF_Pos (17U)
14196 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
14197 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
14200 /******************* Bit definition for TIM_EGR register ********************/
14201 #define TIM_EGR_UG_Pos (0U)
14202 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
14203 #define TIM_EGR_UG TIM_EGR_UG_Msk
14204 #define TIM_EGR_CC1G_Pos (1U)
14205 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
14206 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
14207 #define TIM_EGR_CC2G_Pos (2U)
14208 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
14209 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
14210 #define TIM_EGR_CC3G_Pos (3U)
14211 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
14212 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
14213 #define TIM_EGR_CC4G_Pos (4U)
14214 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
14215 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
14216 #define TIM_EGR_COMG_Pos (5U)
14217 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
14218 #define TIM_EGR_COMG TIM_EGR_COMG_Msk
14219 #define TIM_EGR_TG_Pos (6U)
14220 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
14221 #define TIM_EGR_TG TIM_EGR_TG_Msk
14222 #define TIM_EGR_BG_Pos (7U)
14223 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
14224 #define TIM_EGR_BG TIM_EGR_BG_Msk
14225 #define TIM_EGR_B2G_Pos (8U)
14226 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
14227 #define TIM_EGR_B2G TIM_EGR_B2G_Msk
14230 /****************** Bit definition for TIM_CCMR1 register *******************/
14231 #define TIM_CCMR1_CC1S_Pos (0U)
14232 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
14233 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
14234 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
14235 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
14237 #define TIM_CCMR1_OC1FE_Pos (2U)
14238 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
14239 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
14240 #define TIM_CCMR1_OC1PE_Pos (3U)
14241 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
14242 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
14244 #define TIM_CCMR1_OC1M_Pos (4U)
14245 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
14246 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
14247 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
14248 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
14249 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
14250 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
14252 #define TIM_CCMR1_OC1CE_Pos (7U)
14253 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
14254 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
14256 #define TIM_CCMR1_CC2S_Pos (8U)
14257 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
14258 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
14259 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
14260 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
14262 #define TIM_CCMR1_OC2FE_Pos (10U)
14263 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
14264 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
14265 #define TIM_CCMR1_OC2PE_Pos (11U)
14266 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
14267 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
14269 #define TIM_CCMR1_OC2M_Pos (12U)
14270 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
14271 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
14272 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
14273 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
14274 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
14275 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
14277 #define TIM_CCMR1_OC2CE_Pos (15U)
14278 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
14279 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
14281 /*----------------------------------------------------------------------------*/
14282 #define TIM_CCMR1_IC1PSC_Pos (2U)
14283 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
14284 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
14285 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
14286 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
14288 #define TIM_CCMR1_IC1F_Pos (4U)
14289 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
14290 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
14291 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
14292 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
14293 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
14294 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
14296 #define TIM_CCMR1_IC2PSC_Pos (10U)
14297 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
14298 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
14299 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
14300 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
14302 #define TIM_CCMR1_IC2F_Pos (12U)
14303 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
14304 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
14305 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
14306 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
14307 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
14308 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
14310 /****************** Bit definition for TIM_CCMR2 register *******************/
14311 #define TIM_CCMR2_CC3S_Pos (0U)
14312 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
14313 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
14314 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
14315 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
14317 #define TIM_CCMR2_OC3FE_Pos (2U)
14318 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
14319 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
14320 #define TIM_CCMR2_OC3PE_Pos (3U)
14321 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
14322 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
14324 #define TIM_CCMR2_OC3M_Pos (4U)
14325 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
14326 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
14327 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
14328 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
14329 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
14330 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
14332 #define TIM_CCMR2_OC3CE_Pos (7U)
14333 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
14334 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
14336 #define TIM_CCMR2_CC4S_Pos (8U)
14337 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
14338 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
14339 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
14340 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
14342 #define TIM_CCMR2_OC4FE_Pos (10U)
14343 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
14344 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
14345 #define TIM_CCMR2_OC4PE_Pos (11U)
14346 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
14347 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
14349 #define TIM_CCMR2_OC4M_Pos (12U)
14350 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
14351 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
14352 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
14353 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
14354 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
14355 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
14357 #define TIM_CCMR2_OC4CE_Pos (15U)
14358 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
14359 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
14361 /*----------------------------------------------------------------------------*/
14362 #define TIM_CCMR2_IC3PSC_Pos (2U)
14363 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
14364 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
14365 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
14366 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
14368 #define TIM_CCMR2_IC3F_Pos (4U)
14369 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
14370 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
14371 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
14372 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
14373 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
14374 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
14376 #define TIM_CCMR2_IC4PSC_Pos (10U)
14377 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
14378 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
14379 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
14380 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
14382 #define TIM_CCMR2_IC4F_Pos (12U)
14383 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
14384 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
14385 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
14386 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
14387 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
14388 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
14390 /****************** Bit definition for TIM_CCMR3 register *******************/
14391 #define TIM_CCMR3_OC5FE_Pos (2U)
14392 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
14393 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
14394 #define TIM_CCMR3_OC5PE_Pos (3U)
14395 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
14396 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
14398 #define TIM_CCMR3_OC5M_Pos (4U)
14399 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
14400 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
14401 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
14402 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
14403 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
14404 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
14406 #define TIM_CCMR3_OC5CE_Pos (7U)
14407 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
14408 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
14410 #define TIM_CCMR3_OC6FE_Pos (10U)
14411 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
14412 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
14413 #define TIM_CCMR3_OC6PE_Pos (11U)
14414 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
14415 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
14417 #define TIM_CCMR3_OC6M_Pos (12U)
14418 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
14419 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
14420 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
14421 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
14422 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
14423 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
14425 #define TIM_CCMR3_OC6CE_Pos (15U)
14426 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
14427 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
14429 /******************* Bit definition for TIM_CCER register *******************/
14430 #define TIM_CCER_CC1E_Pos (0U)
14431 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
14432 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
14433 #define TIM_CCER_CC1P_Pos (1U)
14434 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
14435 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
14436 #define TIM_CCER_CC1NE_Pos (2U)
14437 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
14438 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
14439 #define TIM_CCER_CC1NP_Pos (3U)
14440 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
14441 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
14442 #define TIM_CCER_CC2E_Pos (4U)
14443 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
14444 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
14445 #define TIM_CCER_CC2P_Pos (5U)
14446 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
14447 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
14448 #define TIM_CCER_CC2NE_Pos (6U)
14449 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
14450 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
14451 #define TIM_CCER_CC2NP_Pos (7U)
14452 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
14453 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
14454 #define TIM_CCER_CC3E_Pos (8U)
14455 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
14456 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
14457 #define TIM_CCER_CC3P_Pos (9U)
14458 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
14459 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
14460 #define TIM_CCER_CC3NE_Pos (10U)
14461 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
14462 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
14463 #define TIM_CCER_CC3NP_Pos (11U)
14464 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
14465 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
14466 #define TIM_CCER_CC4E_Pos (12U)
14467 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
14468 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
14469 #define TIM_CCER_CC4P_Pos (13U)
14470 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
14471 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
14472 #define TIM_CCER_CC4NP_Pos (15U)
14473 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
14474 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
14475 #define TIM_CCER_CC5E_Pos (16U)
14476 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
14477 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
14478 #define TIM_CCER_CC5P_Pos (17U)
14479 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
14480 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
14481 #define TIM_CCER_CC6E_Pos (20U)
14482 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
14483 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
14484 #define TIM_CCER_CC6P_Pos (21U)
14485 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
14486 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
14488 /******************* Bit definition for TIM_CNT register ********************/
14489 #define TIM_CNT_CNT_Pos (0U)
14490 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
14491 #define TIM_CNT_CNT TIM_CNT_CNT_Msk
14492 #define TIM_CNT_UIFCPY_Pos (31U)
14493 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
14494 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
14496 /******************* Bit definition for TIM_PSC register ********************/
14497 #define TIM_PSC_PSC_Pos (0U)
14498 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
14499 #define TIM_PSC_PSC TIM_PSC_PSC_Msk
14501 /******************* Bit definition for TIM_ARR register ********************/
14502 #define TIM_ARR_ARR_Pos (0U)
14503 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
14504 #define TIM_ARR_ARR TIM_ARR_ARR_Msk
14506 /******************* Bit definition for TIM_RCR register ********************/
14507 #define TIM_RCR_REP_Pos (0U)
14508 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
14509 #define TIM_RCR_REP TIM_RCR_REP_Msk
14511 /******************* Bit definition for TIM_CCR1 register *******************/
14512 #define TIM_CCR1_CCR1_Pos (0U)
14513 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
14514 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
14516 /******************* Bit definition for TIM_CCR2 register *******************/
14517 #define TIM_CCR2_CCR2_Pos (0U)
14518 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
14519 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
14521 /******************* Bit definition for TIM_CCR3 register *******************/
14522 #define TIM_CCR3_CCR3_Pos (0U)
14523 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
14524 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
14526 /******************* Bit definition for TIM_CCR4 register *******************/
14527 #define TIM_CCR4_CCR4_Pos (0U)
14528 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
14529 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
14531 /******************* Bit definition for TIM_CCR5 register *******************/
14532 #define TIM_CCR5_CCR5_Pos (0U)
14533 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
14534 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
14535 #define TIM_CCR5_GC5C1_Pos (29U)
14536 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
14537 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
14538 #define TIM_CCR5_GC5C2_Pos (30U)
14539 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
14540 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
14541 #define TIM_CCR5_GC5C3_Pos (31U)
14542 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
14543 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
14545 /******************* Bit definition for TIM_CCR6 register *******************/
14546 #define TIM_CCR6_CCR6_Pos (0U)
14547 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
14548 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
14550 /******************* Bit definition for TIM_BDTR register *******************/
14551 #define TIM_BDTR_DTG_Pos (0U)
14552 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
14553 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
14554 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
14555 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
14556 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
14557 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
14558 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
14559 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
14560 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
14561 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
14563 #define TIM_BDTR_LOCK_Pos (8U)
14564 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
14565 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
14566 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
14567 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
14569 #define TIM_BDTR_OSSI_Pos (10U)
14570 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
14571 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
14572 #define TIM_BDTR_OSSR_Pos (11U)
14573 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
14574 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
14575 #define TIM_BDTR_BKE_Pos (12U)
14576 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
14577 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
14578 #define TIM_BDTR_BKP_Pos (13U)
14579 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
14580 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
14581 #define TIM_BDTR_AOE_Pos (14U)
14582 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
14583 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
14584 #define TIM_BDTR_MOE_Pos (15U)
14585 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
14586 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
14588 #define TIM_BDTR_BKF_Pos (16U)
14589 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
14590 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
14591 #define TIM_BDTR_BK2F_Pos (20U)
14592 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
14593 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
14595 #define TIM_BDTR_BK2E_Pos (24U)
14596 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
14597 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
14598 #define TIM_BDTR_BK2P_Pos (25U)
14599 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
14600 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
14602 /******************* Bit definition for TIM_DCR register ********************/
14603 #define TIM_DCR_DBA_Pos (0U)
14604 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
14605 #define TIM_DCR_DBA TIM_DCR_DBA_Msk
14606 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
14607 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
14608 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
14609 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
14610 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
14612 #define TIM_DCR_DBL_Pos (8U)
14613 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
14614 #define TIM_DCR_DBL TIM_DCR_DBL_Msk
14615 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
14616 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
14617 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
14618 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
14619 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
14621 /******************* Bit definition for TIM_DMAR register *******************/
14622 #define TIM_DMAR_DMAB_Pos (0U)
14623 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
14624 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
14626 /******************* Bit definition for TIM1_OR1 register *******************/
14627 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
14628 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
14629 #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk
14630 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
14631 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
14633 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U)
14634 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
14635 #define TIM1_OR1_ETR_ADC3_RMP TIM1_OR1_ETR_ADC3_RMP_Msk
14636 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
14637 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
14639 #define TIM1_OR1_TI1_RMP_Pos (4U)
14640 #define TIM1_OR1_TI1_RMP_Msk (0x1UL << TIM1_OR1_TI1_RMP_Pos)
14641 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk
14643 /******************* Bit definition for TIM1_OR2 register *******************/
14644 #define TIM1_OR2_BKINE_Pos (0U)
14645 #define TIM1_OR2_BKINE_Msk (0x1UL << TIM1_OR2_BKINE_Pos)
14646 #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk
14647 #define TIM1_OR2_BKCMP1E_Pos (1U)
14648 #define TIM1_OR2_BKCMP1E_Msk (0x1UL << TIM1_OR2_BKCMP1E_Pos)
14649 #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk
14650 #define TIM1_OR2_BKCMP2E_Pos (2U)
14651 #define TIM1_OR2_BKCMP2E_Msk (0x1UL << TIM1_OR2_BKCMP2E_Pos)
14652 #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk
14653 #define TIM1_OR2_BKDF1BK0E_Pos (8U)
14654 #define TIM1_OR2_BKDF1BK0E_Msk (0x1UL << TIM1_OR2_BKDF1BK0E_Pos)
14655 #define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk
14656 #define TIM1_OR2_BKINP_Pos (9U)
14657 #define TIM1_OR2_BKINP_Msk (0x1UL << TIM1_OR2_BKINP_Pos)
14658 #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk
14659 #define TIM1_OR2_BKCMP1P_Pos (10U)
14660 #define TIM1_OR2_BKCMP1P_Msk (0x1UL << TIM1_OR2_BKCMP1P_Pos)
14661 #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk
14662 #define TIM1_OR2_BKCMP2P_Pos (11U)
14663 #define TIM1_OR2_BKCMP2P_Msk (0x1UL << TIM1_OR2_BKCMP2P_Pos)
14664 #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk
14666 #define TIM1_OR2_ETRSEL_Pos (14U)
14667 #define TIM1_OR2_ETRSEL_Msk (0x7UL << TIM1_OR2_ETRSEL_Pos)
14668 #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk
14669 #define TIM1_OR2_ETRSEL_0 (0x1UL << TIM1_OR2_ETRSEL_Pos)
14670 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos)
14671 #define TIM1_OR2_ETRSEL_2 (0x4UL << TIM1_OR2_ETRSEL_Pos)
14673 /******************* Bit definition for TIM1_OR3 register *******************/
14674 #define TIM1_OR3_BK2INE_Pos (0U)
14675 #define TIM1_OR3_BK2INE_Msk (0x1UL << TIM1_OR3_BK2INE_Pos)
14676 #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk
14677 #define TIM1_OR3_BK2CMP1E_Pos (1U)
14678 #define TIM1_OR3_BK2CMP1E_Msk (0x1UL << TIM1_OR3_BK2CMP1E_Pos)
14679 #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk
14680 #define TIM1_OR3_BK2CMP2E_Pos (2U)
14681 #define TIM1_OR3_BK2CMP2E_Msk (0x1UL << TIM1_OR3_BK2CMP2E_Pos)
14682 #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk
14683 #define TIM1_OR3_BK2DF1BK1E_Pos (8U)
14684 #define TIM1_OR3_BK2DF1BK1E_Msk (0x1UL << TIM1_OR3_BK2DF1BK1E_Pos)
14685 #define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk
14686 #define TIM1_OR3_BK2INP_Pos (9U)
14687 #define TIM1_OR3_BK2INP_Msk (0x1UL << TIM1_OR3_BK2INP_Pos)
14688 #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk
14689 #define TIM1_OR3_BK2CMP1P_Pos (10U)
14690 #define TIM1_OR3_BK2CMP1P_Msk (0x1UL << TIM1_OR3_BK2CMP1P_Pos)
14691 #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk
14692 #define TIM1_OR3_BK2CMP2P_Pos (11U)
14693 #define TIM1_OR3_BK2CMP2P_Msk (0x1UL << TIM1_OR3_BK2CMP2P_Pos)
14694 #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk
14696 /******************* Bit definition for TIM8_OR1 register *******************/
14697 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U)
14698 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
14699 #define TIM8_OR1_ETR_ADC2_RMP TIM8_OR1_ETR_ADC2_RMP_Msk
14700 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
14701 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
14703 #define TIM8_OR1_ETR_ADC3_RMP_Pos (2U)
14704 #define TIM8_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
14705 #define TIM8_OR1_ETR_ADC3_RMP TIM8_OR1_ETR_ADC3_RMP_Msk
14706 #define TIM8_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
14707 #define TIM8_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
14709 #define TIM8_OR1_TI1_RMP_Pos (4U)
14710 #define TIM8_OR1_TI1_RMP_Msk (0x1UL << TIM8_OR1_TI1_RMP_Pos)
14711 #define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk
14713 /******************* Bit definition for TIM8_OR2 register *******************/
14714 #define TIM8_OR2_BKINE_Pos (0U)
14715 #define TIM8_OR2_BKINE_Msk (0x1UL << TIM8_OR2_BKINE_Pos)
14716 #define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk
14717 #define TIM8_OR2_BKCMP1E_Pos (1U)
14718 #define TIM8_OR2_BKCMP1E_Msk (0x1UL << TIM8_OR2_BKCMP1E_Pos)
14719 #define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk
14720 #define TIM8_OR2_BKCMP2E_Pos (2U)
14721 #define TIM8_OR2_BKCMP2E_Msk (0x1UL << TIM8_OR2_BKCMP2E_Pos)
14722 #define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk
14723 #define TIM8_OR2_BKDF1BK2E_Pos (8U)
14724 #define TIM8_OR2_BKDF1BK2E_Msk (0x1UL << TIM8_OR2_BKDF1BK2E_Pos)
14725 #define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk
14726 #define TIM8_OR2_BKINP_Pos (9U)
14727 #define TIM8_OR2_BKINP_Msk (0x1UL << TIM8_OR2_BKINP_Pos)
14728 #define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk
14729 #define TIM8_OR2_BKCMP1P_Pos (10U)
14730 #define TIM8_OR2_BKCMP1P_Msk (0x1UL << TIM8_OR2_BKCMP1P_Pos)
14731 #define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk
14732 #define TIM8_OR2_BKCMP2P_Pos (11U)
14733 #define TIM8_OR2_BKCMP2P_Msk (0x1UL << TIM8_OR2_BKCMP2P_Pos)
14734 #define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk
14736 #define TIM8_OR2_ETRSEL_Pos (14U)
14737 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos)
14738 #define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk
14739 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos)
14740 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos)
14741 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos)
14743 /******************* Bit definition for TIM8_OR3 register *******************/
14744 #define TIM8_OR3_BK2INE_Pos (0U)
14745 #define TIM8_OR3_BK2INE_Msk (0x1UL << TIM8_OR3_BK2INE_Pos)
14746 #define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk
14747 #define TIM8_OR3_BK2CMP1E_Pos (1U)
14748 #define TIM8_OR3_BK2CMP1E_Msk (0x1UL << TIM8_OR3_BK2CMP1E_Pos)
14749 #define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk
14750 #define TIM8_OR3_BK2CMP2E_Pos (2U)
14751 #define TIM8_OR3_BK2CMP2E_Msk (0x1UL << TIM8_OR3_BK2CMP2E_Pos)
14752 #define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk
14753 #define TIM8_OR3_BK2DF1BK3E_Pos (8U)
14754 #define TIM8_OR3_BK2DF1BK3E_Msk (0x1UL << TIM8_OR3_BK2DF1BK3E_Pos)
14755 #define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk
14756 #define TIM8_OR3_BK2INP_Pos (9U)
14757 #define TIM8_OR3_BK2INP_Msk (0x1UL << TIM8_OR3_BK2INP_Pos)
14758 #define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk
14759 #define TIM8_OR3_BK2CMP1P_Pos (10U)
14760 #define TIM8_OR3_BK2CMP1P_Msk (0x1UL << TIM8_OR3_BK2CMP1P_Pos)
14761 #define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk
14762 #define TIM8_OR3_BK2CMP2P_Pos (11U)
14763 #define TIM8_OR3_BK2CMP2P_Msk (0x1UL << TIM8_OR3_BK2CMP2P_Pos)
14764 #define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk
14766 /******************* Bit definition for TIM2_OR1 register *******************/
14767 #define TIM2_OR1_ITR1_RMP_Pos (0U)
14768 #define TIM2_OR1_ITR1_RMP_Msk (0x1UL << TIM2_OR1_ITR1_RMP_Pos)
14769 #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk
14770 #define TIM2_OR1_ETR1_RMP_Pos (1U)
14771 #define TIM2_OR1_ETR1_RMP_Msk (0x1UL << TIM2_OR1_ETR1_RMP_Pos)
14772 #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk
14774 #define TIM2_OR1_TI4_RMP_Pos (2U)
14775 #define TIM2_OR1_TI4_RMP_Msk (0x3UL << TIM2_OR1_TI4_RMP_Pos)
14776 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk
14777 #define TIM2_OR1_TI4_RMP_0 (0x1UL << TIM2_OR1_TI4_RMP_Pos)
14778 #define TIM2_OR1_TI4_RMP_1 (0x2UL << TIM2_OR1_TI4_RMP_Pos)
14780 /******************* Bit definition for TIM2_OR2 register *******************/
14781 #define TIM2_OR2_ETRSEL_Pos (14U)
14782 #define TIM2_OR2_ETRSEL_Msk (0x7UL << TIM2_OR2_ETRSEL_Pos)
14783 #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk
14784 #define TIM2_OR2_ETRSEL_0 (0x1UL << TIM2_OR2_ETRSEL_Pos)
14785 #define TIM2_OR2_ETRSEL_1 (0x2UL << TIM2_OR2_ETRSEL_Pos)
14786 #define TIM2_OR2_ETRSEL_2 (0x4UL << TIM2_OR2_ETRSEL_Pos)
14788 /******************* Bit definition for TIM3_OR1 register *******************/
14789 #define TIM3_OR1_TI1_RMP_Pos (0U)
14790 #define TIM3_OR1_TI1_RMP_Msk (0x3UL << TIM3_OR1_TI1_RMP_Pos)
14791 #define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk
14792 #define TIM3_OR1_TI1_RMP_0 (0x1UL << TIM3_OR1_TI1_RMP_Pos)
14793 #define TIM3_OR1_TI1_RMP_1 (0x2UL << TIM3_OR1_TI1_RMP_Pos)
14795 /******************* Bit definition for TIM3_OR2 register *******************/
14796 #define TIM3_OR2_ETRSEL_Pos (14U)
14797 #define TIM3_OR2_ETRSEL_Msk (0x7UL << TIM3_OR2_ETRSEL_Pos)
14798 #define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk
14799 #define TIM3_OR2_ETRSEL_0 (0x1UL << TIM3_OR2_ETRSEL_Pos)
14800 #define TIM3_OR2_ETRSEL_1 (0x2UL << TIM3_OR2_ETRSEL_Pos)
14801 #define TIM3_OR2_ETRSEL_2 (0x4UL << TIM3_OR2_ETRSEL_Pos)
14803 /******************* Bit definition for TIM15_OR1 register ******************/
14804 #define TIM15_OR1_TI1_RMP_Pos (0U)
14805 #define TIM15_OR1_TI1_RMP_Msk (0x1UL << TIM15_OR1_TI1_RMP_Pos)
14806 #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk
14808 #define TIM15_OR1_ENCODER_MODE_Pos (1U)
14809 #define TIM15_OR1_ENCODER_MODE_Msk (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)
14810 #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk
14811 #define TIM15_OR1_ENCODER_MODE_0 (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)
14812 #define TIM15_OR1_ENCODER_MODE_1 (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)
14814 /******************* Bit definition for TIM15_OR2 register ******************/
14815 #define TIM15_OR2_BKINE_Pos (0U)
14816 #define TIM15_OR2_BKINE_Msk (0x1UL << TIM15_OR2_BKINE_Pos)
14817 #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk
14818 #define TIM15_OR2_BKCMP1E_Pos (1U)
14819 #define TIM15_OR2_BKCMP1E_Msk (0x1UL << TIM15_OR2_BKCMP1E_Pos)
14820 #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk
14821 #define TIM15_OR2_BKCMP2E_Pos (2U)
14822 #define TIM15_OR2_BKCMP2E_Msk (0x1UL << TIM15_OR2_BKCMP2E_Pos)
14823 #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk
14824 #define TIM15_OR2_BKDF1BK0E_Pos (8U)
14825 #define TIM15_OR2_BKDF1BK0E_Msk (0x1UL << TIM15_OR2_BKDF1BK0E_Pos)
14826 #define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk
14827 #define TIM15_OR2_BKINP_Pos (9U)
14828 #define TIM15_OR2_BKINP_Msk (0x1UL << TIM15_OR2_BKINP_Pos)
14829 #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk
14830 #define TIM15_OR2_BKCMP1P_Pos (10U)
14831 #define TIM15_OR2_BKCMP1P_Msk (0x1UL << TIM15_OR2_BKCMP1P_Pos)
14832 #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk
14833 #define TIM15_OR2_BKCMP2P_Pos (11U)
14834 #define TIM15_OR2_BKCMP2P_Msk (0x1UL << TIM15_OR2_BKCMP2P_Pos)
14835 #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk
14837 /******************* Bit definition for TIM16_OR1 register ******************/
14838 #define TIM16_OR1_TI1_RMP_Pos (0U)
14839 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos)
14840 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk
14841 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos)
14842 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos)
14844 /******************* Bit definition for TIM16_OR2 register ******************/
14845 #define TIM16_OR2_BKINE_Pos (0U)
14846 #define TIM16_OR2_BKINE_Msk (0x1UL << TIM16_OR2_BKINE_Pos)
14847 #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk
14848 #define TIM16_OR2_BKCMP1E_Pos (1U)
14849 #define TIM16_OR2_BKCMP1E_Msk (0x1UL << TIM16_OR2_BKCMP1E_Pos)
14850 #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk
14851 #define TIM16_OR2_BKCMP2E_Pos (2U)
14852 #define TIM16_OR2_BKCMP2E_Msk (0x1UL << TIM16_OR2_BKCMP2E_Pos)
14853 #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk
14854 #define TIM16_OR2_BKDF1BK1E_Pos (8U)
14855 #define TIM16_OR2_BKDF1BK1E_Msk (0x1UL << TIM16_OR2_BKDF1BK1E_Pos)
14856 #define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk
14857 #define TIM16_OR2_BKINP_Pos (9U)
14858 #define TIM16_OR2_BKINP_Msk (0x1UL << TIM16_OR2_BKINP_Pos)
14859 #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk
14860 #define TIM16_OR2_BKCMP1P_Pos (10U)
14861 #define TIM16_OR2_BKCMP1P_Msk (0x1UL << TIM16_OR2_BKCMP1P_Pos)
14862 #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk
14863 #define TIM16_OR2_BKCMP2P_Pos (11U)
14864 #define TIM16_OR2_BKCMP2P_Msk (0x1UL << TIM16_OR2_BKCMP2P_Pos)
14865 #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk
14867 /******************* Bit definition for TIM17_OR1 register ******************/
14868 #define TIM17_OR1_TI1_RMP_Pos (0U)
14869 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos)
14870 #define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk
14871 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos)
14872 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos)
14874 /******************* Bit definition for TIM17_OR2 register ******************/
14875 #define TIM17_OR2_BKINE_Pos (0U)
14876 #define TIM17_OR2_BKINE_Msk (0x1UL << TIM17_OR2_BKINE_Pos)
14877 #define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk
14878 #define TIM17_OR2_BKCMP1E_Pos (1U)
14879 #define TIM17_OR2_BKCMP1E_Msk (0x1UL << TIM17_OR2_BKCMP1E_Pos)
14880 #define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk
14881 #define TIM17_OR2_BKCMP2E_Pos (2U)
14882 #define TIM17_OR2_BKCMP2E_Msk (0x1UL << TIM17_OR2_BKCMP2E_Pos)
14883 #define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk
14884 #define TIM17_OR2_BKDF1BK2E_Pos (8U)
14885 #define TIM17_OR2_BKDF1BK2E_Msk (0x1UL << TIM17_OR2_BKDF1BK2E_Pos)
14886 #define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk
14887 #define TIM17_OR2_BKINP_Pos (9U)
14888 #define TIM17_OR2_BKINP_Msk (0x1UL << TIM17_OR2_BKINP_Pos)
14889 #define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk
14890 #define TIM17_OR2_BKCMP1P_Pos (10U)
14891 #define TIM17_OR2_BKCMP1P_Msk (0x1UL << TIM17_OR2_BKCMP1P_Pos)
14892 #define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk
14893 #define TIM17_OR2_BKCMP2P_Pos (11U)
14894 #define TIM17_OR2_BKCMP2P_Msk (0x1UL << TIM17_OR2_BKCMP2P_Pos)
14895 #define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk
14897 /******************************************************************************/
14898 /* */
14899 /* Low Power Timer (LPTTIM) */
14900 /* */
14901 /******************************************************************************/
14902 /****************** Bit definition for LPTIM_ISR register *******************/
14903 #define LPTIM_ISR_CMPM_Pos (0U)
14904 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
14905 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
14906 #define LPTIM_ISR_ARRM_Pos (1U)
14907 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
14908 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
14909 #define LPTIM_ISR_EXTTRIG_Pos (2U)
14910 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
14911 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
14912 #define LPTIM_ISR_CMPOK_Pos (3U)
14913 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
14914 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
14915 #define LPTIM_ISR_ARROK_Pos (4U)
14916 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
14917 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
14918 #define LPTIM_ISR_UP_Pos (5U)
14919 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
14920 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
14921 #define LPTIM_ISR_DOWN_Pos (6U)
14922 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
14923 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
14925 /****************** Bit definition for LPTIM_ICR register *******************/
14926 #define LPTIM_ICR_CMPMCF_Pos (0U)
14927 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
14928 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
14929 #define LPTIM_ICR_ARRMCF_Pos (1U)
14930 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
14931 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
14932 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
14933 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
14934 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
14935 #define LPTIM_ICR_CMPOKCF_Pos (3U)
14936 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
14937 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
14938 #define LPTIM_ICR_ARROKCF_Pos (4U)
14939 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
14940 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
14941 #define LPTIM_ICR_UPCF_Pos (5U)
14942 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
14943 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
14944 #define LPTIM_ICR_DOWNCF_Pos (6U)
14945 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
14946 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
14948 /****************** Bit definition for LPTIM_IER register ********************/
14949 #define LPTIM_IER_CMPMIE_Pos (0U)
14950 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
14951 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
14952 #define LPTIM_IER_ARRMIE_Pos (1U)
14953 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
14954 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
14955 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
14956 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
14957 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
14958 #define LPTIM_IER_CMPOKIE_Pos (3U)
14959 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
14960 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
14961 #define LPTIM_IER_ARROKIE_Pos (4U)
14962 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
14963 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
14964 #define LPTIM_IER_UPIE_Pos (5U)
14965 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
14966 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
14967 #define LPTIM_IER_DOWNIE_Pos (6U)
14968 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
14969 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
14971 /****************** Bit definition for LPTIM_CFGR register *******************/
14972 #define LPTIM_CFGR_CKSEL_Pos (0U)
14973 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
14974 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
14976 #define LPTIM_CFGR_CKPOL_Pos (1U)
14977 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
14978 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
14979 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
14980 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
14982 #define LPTIM_CFGR_CKFLT_Pos (3U)
14983 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
14984 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
14985 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
14986 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
14988 #define LPTIM_CFGR_TRGFLT_Pos (6U)
14989 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
14990 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
14991 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
14992 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
14994 #define LPTIM_CFGR_PRESC_Pos (9U)
14995 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
14996 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
14997 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
14998 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
14999 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
15001 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
15002 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
15003 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
15004 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
15005 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
15006 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
15008 #define LPTIM_CFGR_TRIGEN_Pos (17U)
15009 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
15010 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
15011 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
15012 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
15014 #define LPTIM_CFGR_TIMOUT_Pos (19U)
15015 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
15016 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
15017 #define LPTIM_CFGR_WAVE_Pos (20U)
15018 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
15019 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
15020 #define LPTIM_CFGR_WAVPOL_Pos (21U)
15021 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
15022 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
15023 #define LPTIM_CFGR_PRELOAD_Pos (22U)
15024 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
15025 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
15026 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
15027 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
15028 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
15029 #define LPTIM_CFGR_ENC_Pos (24U)
15030 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
15031 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
15033 /****************** Bit definition for LPTIM_CR register ********************/
15034 #define LPTIM_CR_ENABLE_Pos (0U)
15035 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
15036 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
15037 #define LPTIM_CR_SNGSTRT_Pos (1U)
15038 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
15039 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
15040 #define LPTIM_CR_CNTSTRT_Pos (2U)
15041 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
15042 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
15044 /****************** Bit definition for LPTIM_CMP register *******************/
15045 #define LPTIM_CMP_CMP_Pos (0U)
15046 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
15047 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
15049 /****************** Bit definition for LPTIM_ARR register *******************/
15050 #define LPTIM_ARR_ARR_Pos (0U)
15051 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
15052 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
15054 /****************** Bit definition for LPTIM_CNT register *******************/
15055 #define LPTIM_CNT_CNT_Pos (0U)
15056 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
15057 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
15059 /****************** Bit definition for LPTIM_OR register ********************/
15060 #define LPTIM_OR_OR_Pos (0U)
15061 #define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos)
15062 #define LPTIM_OR_OR LPTIM_OR_OR_Msk
15063 #define LPTIM_OR_OR_0 (0x1UL << LPTIM_OR_OR_Pos)
15064 #define LPTIM_OR_OR_1 (0x2UL << LPTIM_OR_OR_Pos)
15066 /******************************************************************************/
15067 /* */
15068 /* Analog Comparators (COMP) */
15069 /* */
15070 /******************************************************************************/
15071 /********************** Bit definition for COMP_CSR register ****************/
15072 #define COMP_CSR_EN_Pos (0U)
15073 #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos)
15074 #define COMP_CSR_EN COMP_CSR_EN_Msk
15076 #define COMP_CSR_PWRMODE_Pos (2U)
15077 #define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos)
15078 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk
15079 #define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos)
15080 #define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos)
15082 #define COMP_CSR_INMSEL_Pos (4U)
15083 #define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos)
15084 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk
15085 #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos)
15086 #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos)
15087 #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos)
15089 #define COMP_CSR_INPSEL_Pos (7U)
15090 #define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos)
15091 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk
15092 #define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos)
15094 #define COMP_CSR_WINMODE_Pos (9U)
15095 #define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos)
15096 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk
15098 #define COMP_CSR_POLARITY_Pos (15U)
15099 #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos)
15100 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk
15102 #define COMP_CSR_HYST_Pos (16U)
15103 #define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos)
15104 #define COMP_CSR_HYST COMP_CSR_HYST_Msk
15105 #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos)
15106 #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos)
15108 #define COMP_CSR_BLANKING_Pos (18U)
15109 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos)
15110 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk
15111 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos)
15112 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos)
15113 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos)
15115 #define COMP_CSR_BRGEN_Pos (22U)
15116 #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos)
15117 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk
15118 #define COMP_CSR_SCALEN_Pos (23U)
15119 #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos)
15120 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk
15122 #define COMP_CSR_VALUE_Pos (30U)
15123 #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos)
15124 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk
15126 #define COMP_CSR_LOCK_Pos (31U)
15127 #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos)
15128 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk
15130 /******************************************************************************/
15131 /* */
15132 /* Operational Amplifier (OPAMP) */
15133 /* */
15134 /******************************************************************************/
15135 /********************* Bit definition for OPAMPx_CSR register ***************/
15136 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
15137 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
15138 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
15139 #define OPAMP_CSR_OPALPM_Pos (1U)
15140 #define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos)
15141 #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk
15143 #define OPAMP_CSR_OPAMODE_Pos (2U)
15144 #define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos)
15145 #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk
15146 #define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos)
15147 #define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos)
15149 #define OPAMP_CSR_PGGAIN_Pos (4U)
15150 #define OPAMP_CSR_PGGAIN_Msk (0x3UL << OPAMP_CSR_PGGAIN_Pos)
15151 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
15152 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
15153 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
15155 #define OPAMP_CSR_VMSEL_Pos (8U)
15156 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
15157 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
15158 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
15159 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
15161 #define OPAMP_CSR_VPSEL_Pos (10U)
15162 #define OPAMP_CSR_VPSEL_Msk (0x1UL << OPAMP_CSR_VPSEL_Pos)
15163 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
15164 #define OPAMP_CSR_CALON_Pos (12U)
15165 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
15166 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
15167 #define OPAMP_CSR_CALSEL_Pos (13U)
15168 #define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos)
15169 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
15170 #define OPAMP_CSR_USERTRIM_Pos (14U)
15171 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
15172 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
15173 #define OPAMP_CSR_CALOUT_Pos (15U)
15174 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
15175 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
15177 /********************* Bit definition for OPAMP1_CSR register ***************/
15178 #define OPAMP1_CSR_OPAEN_Pos (0U)
15179 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
15180 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
15181 #define OPAMP1_CSR_OPALPM_Pos (1U)
15182 #define OPAMP1_CSR_OPALPM_Msk (0x1UL << OPAMP1_CSR_OPALPM_Pos)
15183 #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk
15185 #define OPAMP1_CSR_OPAMODE_Pos (2U)
15186 #define OPAMP1_CSR_OPAMODE_Msk (0x3UL << OPAMP1_CSR_OPAMODE_Pos)
15187 #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk
15188 #define OPAMP1_CSR_OPAMODE_0 (0x1UL << OPAMP1_CSR_OPAMODE_Pos)
15189 #define OPAMP1_CSR_OPAMODE_1 (0x2UL << OPAMP1_CSR_OPAMODE_Pos)
15191 #define OPAMP1_CSR_PGAGAIN_Pos (4U)
15192 #define OPAMP1_CSR_PGAGAIN_Msk (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)
15193 #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk
15194 #define OPAMP1_CSR_PGAGAIN_0 (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)
15195 #define OPAMP1_CSR_PGAGAIN_1 (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)
15197 #define OPAMP1_CSR_VMSEL_Pos (8U)
15198 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
15199 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
15200 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
15201 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
15203 #define OPAMP1_CSR_VPSEL_Pos (10U)
15204 #define OPAMP1_CSR_VPSEL_Msk (0x1UL << OPAMP1_CSR_VPSEL_Pos)
15205 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
15206 #define OPAMP1_CSR_CALON_Pos (12U)
15207 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
15208 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
15209 #define OPAMP1_CSR_CALSEL_Pos (13U)
15210 #define OPAMP1_CSR_CALSEL_Msk (0x1UL << OPAMP1_CSR_CALSEL_Pos)
15211 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
15212 #define OPAMP1_CSR_USERTRIM_Pos (14U)
15213 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
15214 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
15215 #define OPAMP1_CSR_CALOUT_Pos (15U)
15216 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
15217 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
15219 #define OPAMP1_CSR_OPARANGE_Pos (31U)
15220 #define OPAMP1_CSR_OPARANGE_Msk (0x1UL << OPAMP1_CSR_OPARANGE_Pos)
15221 #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk
15223 /********************* Bit definition for OPAMP2_CSR register ***************/
15224 #define OPAMP2_CSR_OPAEN_Pos (0U)
15225 #define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
15226 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
15227 #define OPAMP2_CSR_OPALPM_Pos (1U)
15228 #define OPAMP2_CSR_OPALPM_Msk (0x1UL << OPAMP2_CSR_OPALPM_Pos)
15229 #define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk
15231 #define OPAMP2_CSR_OPAMODE_Pos (2U)
15232 #define OPAMP2_CSR_OPAMODE_Msk (0x3UL << OPAMP2_CSR_OPAMODE_Pos)
15233 #define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk
15234 #define OPAMP2_CSR_OPAMODE_0 (0x1UL << OPAMP2_CSR_OPAMODE_Pos)
15235 #define OPAMP2_CSR_OPAMODE_1 (0x2UL << OPAMP2_CSR_OPAMODE_Pos)
15237 #define OPAMP2_CSR_PGAGAIN_Pos (4U)
15238 #define OPAMP2_CSR_PGAGAIN_Msk (0x3UL << OPAMP2_CSR_PGAGAIN_Pos)
15239 #define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk
15240 #define OPAMP2_CSR_PGAGAIN_0 (0x1UL << OPAMP2_CSR_PGAGAIN_Pos)
15241 #define OPAMP2_CSR_PGAGAIN_1 (0x2UL << OPAMP2_CSR_PGAGAIN_Pos)
15243 #define OPAMP2_CSR_VMSEL_Pos (8U)
15244 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
15245 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
15246 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
15247 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
15249 #define OPAMP2_CSR_VPSEL_Pos (10U)
15250 #define OPAMP2_CSR_VPSEL_Msk (0x1UL << OPAMP2_CSR_VPSEL_Pos)
15251 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
15252 #define OPAMP2_CSR_CALON_Pos (12U)
15253 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
15254 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
15255 #define OPAMP2_CSR_CALSEL_Pos (13U)
15256 #define OPAMP2_CSR_CALSEL_Msk (0x1UL << OPAMP2_CSR_CALSEL_Pos)
15257 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
15258 #define OPAMP2_CSR_USERTRIM_Pos (14U)
15259 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
15260 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
15261 #define OPAMP2_CSR_CALOUT_Pos (15U)
15262 #define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
15263 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
15265 /******************* Bit definition for OPAMP_OTR register ******************/
15266 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
15267 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
15268 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
15269 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
15270 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
15271 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
15273 /******************* Bit definition for OPAMP1_OTR register ******************/
15274 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
15275 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
15276 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
15277 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
15278 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
15279 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
15281 /******************* Bit definition for OPAMP2_OTR register ******************/
15282 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
15283 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
15284 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
15285 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
15286 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
15287 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
15289 /******************* Bit definition for OPAMP_LPOTR register ****************/
15290 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
15291 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos)
15292 #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk
15293 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
15294 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos)
15295 #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk
15297 /******************* Bit definition for OPAMP1_LPOTR register ****************/
15298 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
15299 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos)
15300 #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk
15301 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
15302 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos)
15303 #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk
15305 /******************* Bit definition for OPAMP2_LPOTR register ****************/
15306 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
15307 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos)
15308 #define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk
15309 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
15310 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos)
15311 #define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk
15313 /******************************************************************************/
15314 /* */
15315 /* Touch Sensing Controller (TSC) */
15316 /* */
15317 /******************************************************************************/
15318 /******************* Bit definition for TSC_CR register *********************/
15319 #define TSC_CR_TSCE_Pos (0U)
15320 #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos)
15321 #define TSC_CR_TSCE TSC_CR_TSCE_Msk
15322 #define TSC_CR_START_Pos (1U)
15323 #define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos)
15324 #define TSC_CR_START TSC_CR_START_Msk
15325 #define TSC_CR_AM_Pos (2U)
15326 #define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos)
15327 #define TSC_CR_AM TSC_CR_AM_Msk
15328 #define TSC_CR_SYNCPOL_Pos (3U)
15329 #define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos)
15330 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk
15331 #define TSC_CR_IODEF_Pos (4U)
15332 #define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos)
15333 #define TSC_CR_IODEF TSC_CR_IODEF_Msk
15335 #define TSC_CR_MCV_Pos (5U)
15336 #define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos)
15337 #define TSC_CR_MCV TSC_CR_MCV_Msk
15338 #define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos)
15339 #define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos)
15340 #define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos)
15342 #define TSC_CR_PGPSC_Pos (12U)
15343 #define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos)
15344 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk
15345 #define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos)
15346 #define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos)
15347 #define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos)
15349 #define TSC_CR_SSPSC_Pos (15U)
15350 #define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos)
15351 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk
15352 #define TSC_CR_SSE_Pos (16U)
15353 #define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos)
15354 #define TSC_CR_SSE TSC_CR_SSE_Msk
15356 #define TSC_CR_SSD_Pos (17U)
15357 #define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos)
15358 #define TSC_CR_SSD TSC_CR_SSD_Msk
15359 #define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos)
15360 #define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos)
15361 #define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos)
15362 #define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos)
15363 #define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos)
15364 #define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos)
15365 #define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos)
15367 #define TSC_CR_CTPL_Pos (24U)
15368 #define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos)
15369 #define TSC_CR_CTPL TSC_CR_CTPL_Msk
15370 #define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos)
15371 #define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos)
15372 #define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos)
15373 #define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos)
15375 #define TSC_CR_CTPH_Pos (28U)
15376 #define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos)
15377 #define TSC_CR_CTPH TSC_CR_CTPH_Msk
15378 #define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos)
15379 #define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos)
15380 #define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos)
15381 #define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos)
15383 /******************* Bit definition for TSC_IER register ********************/
15384 #define TSC_IER_EOAIE_Pos (0U)
15385 #define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos)
15386 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk
15387 #define TSC_IER_MCEIE_Pos (1U)
15388 #define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos)
15389 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk
15391 /******************* Bit definition for TSC_ICR register ********************/
15392 #define TSC_ICR_EOAIC_Pos (0U)
15393 #define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos)
15394 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk
15395 #define TSC_ICR_MCEIC_Pos (1U)
15396 #define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos)
15397 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk
15399 /******************* Bit definition for TSC_ISR register ********************/
15400 #define TSC_ISR_EOAF_Pos (0U)
15401 #define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos)
15402 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk
15403 #define TSC_ISR_MCEF_Pos (1U)
15404 #define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos)
15405 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk
15407 /******************* Bit definition for TSC_IOHCR register ******************/
15408 #define TSC_IOHCR_G1_IO1_Pos (0U)
15409 #define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos)
15410 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk
15411 #define TSC_IOHCR_G1_IO2_Pos (1U)
15412 #define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos)
15413 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk
15414 #define TSC_IOHCR_G1_IO3_Pos (2U)
15415 #define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos)
15416 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk
15417 #define TSC_IOHCR_G1_IO4_Pos (3U)
15418 #define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos)
15419 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk
15420 #define TSC_IOHCR_G2_IO1_Pos (4U)
15421 #define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos)
15422 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk
15423 #define TSC_IOHCR_G2_IO2_Pos (5U)
15424 #define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos)
15425 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk
15426 #define TSC_IOHCR_G2_IO3_Pos (6U)
15427 #define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos)
15428 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk
15429 #define TSC_IOHCR_G2_IO4_Pos (7U)
15430 #define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos)
15431 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk
15432 #define TSC_IOHCR_G3_IO1_Pos (8U)
15433 #define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos)
15434 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk
15435 #define TSC_IOHCR_G3_IO2_Pos (9U)
15436 #define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos)
15437 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk
15438 #define TSC_IOHCR_G3_IO3_Pos (10U)
15439 #define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos)
15440 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk
15441 #define TSC_IOHCR_G3_IO4_Pos (11U)
15442 #define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos)
15443 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk
15444 #define TSC_IOHCR_G4_IO1_Pos (12U)
15445 #define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos)
15446 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk
15447 #define TSC_IOHCR_G4_IO2_Pos (13U)
15448 #define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos)
15449 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk
15450 #define TSC_IOHCR_G4_IO3_Pos (14U)
15451 #define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos)
15452 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk
15453 #define TSC_IOHCR_G4_IO4_Pos (15U)
15454 #define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos)
15455 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk
15456 #define TSC_IOHCR_G5_IO1_Pos (16U)
15457 #define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos)
15458 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk
15459 #define TSC_IOHCR_G5_IO2_Pos (17U)
15460 #define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos)
15461 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk
15462 #define TSC_IOHCR_G5_IO3_Pos (18U)
15463 #define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos)
15464 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk
15465 #define TSC_IOHCR_G5_IO4_Pos (19U)
15466 #define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos)
15467 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk
15468 #define TSC_IOHCR_G6_IO1_Pos (20U)
15469 #define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos)
15470 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk
15471 #define TSC_IOHCR_G6_IO2_Pos (21U)
15472 #define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos)
15473 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk
15474 #define TSC_IOHCR_G6_IO3_Pos (22U)
15475 #define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos)
15476 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk
15477 #define TSC_IOHCR_G6_IO4_Pos (23U)
15478 #define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos)
15479 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk
15480 #define TSC_IOHCR_G7_IO1_Pos (24U)
15481 #define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos)
15482 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk
15483 #define TSC_IOHCR_G7_IO2_Pos (25U)
15484 #define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos)
15485 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk
15486 #define TSC_IOHCR_G7_IO3_Pos (26U)
15487 #define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos)
15488 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk
15489 #define TSC_IOHCR_G7_IO4_Pos (27U)
15490 #define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos)
15491 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk
15492 #define TSC_IOHCR_G8_IO1_Pos (28U)
15493 #define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos)
15494 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk
15495 #define TSC_IOHCR_G8_IO2_Pos (29U)
15496 #define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos)
15497 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk
15498 #define TSC_IOHCR_G8_IO3_Pos (30U)
15499 #define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos)
15500 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk
15501 #define TSC_IOHCR_G8_IO4_Pos (31U)
15502 #define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos)
15503 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk
15505 /******************* Bit definition for TSC_IOASCR register *****************/
15506 #define TSC_IOASCR_G1_IO1_Pos (0U)
15507 #define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos)
15508 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk
15509 #define TSC_IOASCR_G1_IO2_Pos (1U)
15510 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos)
15511 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk
15512 #define TSC_IOASCR_G1_IO3_Pos (2U)
15513 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos)
15514 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk
15515 #define TSC_IOASCR_G1_IO4_Pos (3U)
15516 #define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos)
15517 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk
15518 #define TSC_IOASCR_G2_IO1_Pos (4U)
15519 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos)
15520 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk
15521 #define TSC_IOASCR_G2_IO2_Pos (5U)
15522 #define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos)
15523 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk
15524 #define TSC_IOASCR_G2_IO3_Pos (6U)
15525 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos)
15526 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk
15527 #define TSC_IOASCR_G2_IO4_Pos (7U)
15528 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos)
15529 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk
15530 #define TSC_IOASCR_G3_IO1_Pos (8U)
15531 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos)
15532 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk
15533 #define TSC_IOASCR_G3_IO2_Pos (9U)
15534 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos)
15535 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk
15536 #define TSC_IOASCR_G3_IO3_Pos (10U)
15537 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos)
15538 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk
15539 #define TSC_IOASCR_G3_IO4_Pos (11U)
15540 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos)
15541 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk
15542 #define TSC_IOASCR_G4_IO1_Pos (12U)
15543 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos)
15544 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk
15545 #define TSC_IOASCR_G4_IO2_Pos (13U)
15546 #define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos)
15547 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk
15548 #define TSC_IOASCR_G4_IO3_Pos (14U)
15549 #define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos)
15550 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk
15551 #define TSC_IOASCR_G4_IO4_Pos (15U)
15552 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos)
15553 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk
15554 #define TSC_IOASCR_G5_IO1_Pos (16U)
15555 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos)
15556 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk
15557 #define TSC_IOASCR_G5_IO2_Pos (17U)
15558 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos)
15559 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk
15560 #define TSC_IOASCR_G5_IO3_Pos (18U)
15561 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos)
15562 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk
15563 #define TSC_IOASCR_G5_IO4_Pos (19U)
15564 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos)
15565 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk
15566 #define TSC_IOASCR_G6_IO1_Pos (20U)
15567 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos)
15568 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk
15569 #define TSC_IOASCR_G6_IO2_Pos (21U)
15570 #define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos)
15571 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk
15572 #define TSC_IOASCR_G6_IO3_Pos (22U)
15573 #define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos)
15574 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk
15575 #define TSC_IOASCR_G6_IO4_Pos (23U)
15576 #define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos)
15577 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk
15578 #define TSC_IOASCR_G7_IO1_Pos (24U)
15579 #define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos)
15580 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk
15581 #define TSC_IOASCR_G7_IO2_Pos (25U)
15582 #define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos)
15583 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk
15584 #define TSC_IOASCR_G7_IO3_Pos (26U)
15585 #define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos)
15586 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk
15587 #define TSC_IOASCR_G7_IO4_Pos (27U)
15588 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos)
15589 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk
15590 #define TSC_IOASCR_G8_IO1_Pos (28U)
15591 #define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos)
15592 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk
15593 #define TSC_IOASCR_G8_IO2_Pos (29U)
15594 #define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos)
15595 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk
15596 #define TSC_IOASCR_G8_IO3_Pos (30U)
15597 #define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos)
15598 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk
15599 #define TSC_IOASCR_G8_IO4_Pos (31U)
15600 #define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos)
15601 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk
15603 /******************* Bit definition for TSC_IOSCR register ******************/
15604 #define TSC_IOSCR_G1_IO1_Pos (0U)
15605 #define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos)
15606 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk
15607 #define TSC_IOSCR_G1_IO2_Pos (1U)
15608 #define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos)
15609 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk
15610 #define TSC_IOSCR_G1_IO3_Pos (2U)
15611 #define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos)
15612 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk
15613 #define TSC_IOSCR_G1_IO4_Pos (3U)
15614 #define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos)
15615 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk
15616 #define TSC_IOSCR_G2_IO1_Pos (4U)
15617 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos)
15618 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk
15619 #define TSC_IOSCR_G2_IO2_Pos (5U)
15620 #define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos)
15621 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk
15622 #define TSC_IOSCR_G2_IO3_Pos (6U)
15623 #define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos)
15624 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk
15625 #define TSC_IOSCR_G2_IO4_Pos (7U)
15626 #define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos)
15627 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk
15628 #define TSC_IOSCR_G3_IO1_Pos (8U)
15629 #define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos)
15630 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk
15631 #define TSC_IOSCR_G3_IO2_Pos (9U)
15632 #define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos)
15633 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk
15634 #define TSC_IOSCR_G3_IO3_Pos (10U)
15635 #define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos)
15636 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk
15637 #define TSC_IOSCR_G3_IO4_Pos (11U)
15638 #define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos)
15639 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk
15640 #define TSC_IOSCR_G4_IO1_Pos (12U)
15641 #define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos)
15642 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk
15643 #define TSC_IOSCR_G4_IO2_Pos (13U)
15644 #define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos)
15645 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk
15646 #define TSC_IOSCR_G4_IO3_Pos (14U)
15647 #define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos)
15648 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk
15649 #define TSC_IOSCR_G4_IO4_Pos (15U)
15650 #define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos)
15651 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk
15652 #define TSC_IOSCR_G5_IO1_Pos (16U)
15653 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos)
15654 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk
15655 #define TSC_IOSCR_G5_IO2_Pos (17U)
15656 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos)
15657 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk
15658 #define TSC_IOSCR_G5_IO3_Pos (18U)
15659 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos)
15660 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk
15661 #define TSC_IOSCR_G5_IO4_Pos (19U)
15662 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos)
15663 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk
15664 #define TSC_IOSCR_G6_IO1_Pos (20U)
15665 #define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos)
15666 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk
15667 #define TSC_IOSCR_G6_IO2_Pos (21U)
15668 #define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos)
15669 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk
15670 #define TSC_IOSCR_G6_IO3_Pos (22U)
15671 #define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos)
15672 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk
15673 #define TSC_IOSCR_G6_IO4_Pos (23U)
15674 #define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos)
15675 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk
15676 #define TSC_IOSCR_G7_IO1_Pos (24U)
15677 #define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos)
15678 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk
15679 #define TSC_IOSCR_G7_IO2_Pos (25U)
15680 #define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos)
15681 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk
15682 #define TSC_IOSCR_G7_IO3_Pos (26U)
15683 #define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos)
15684 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk
15685 #define TSC_IOSCR_G7_IO4_Pos (27U)
15686 #define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos)
15687 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk
15688 #define TSC_IOSCR_G8_IO1_Pos (28U)
15689 #define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos)
15690 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk
15691 #define TSC_IOSCR_G8_IO2_Pos (29U)
15692 #define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos)
15693 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk
15694 #define TSC_IOSCR_G8_IO3_Pos (30U)
15695 #define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos)
15696 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk
15697 #define TSC_IOSCR_G8_IO4_Pos (31U)
15698 #define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos)
15699 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk
15701 /******************* Bit definition for TSC_IOCCR register ******************/
15702 #define TSC_IOCCR_G1_IO1_Pos (0U)
15703 #define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos)
15704 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk
15705 #define TSC_IOCCR_G1_IO2_Pos (1U)
15706 #define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos)
15707 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk
15708 #define TSC_IOCCR_G1_IO3_Pos (2U)
15709 #define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos)
15710 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk
15711 #define TSC_IOCCR_G1_IO4_Pos (3U)
15712 #define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos)
15713 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk
15714 #define TSC_IOCCR_G2_IO1_Pos (4U)
15715 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos)
15716 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk
15717 #define TSC_IOCCR_G2_IO2_Pos (5U)
15718 #define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos)
15719 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk
15720 #define TSC_IOCCR_G2_IO3_Pos (6U)
15721 #define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos)
15722 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk
15723 #define TSC_IOCCR_G2_IO4_Pos (7U)
15724 #define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos)
15725 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk
15726 #define TSC_IOCCR_G3_IO1_Pos (8U)
15727 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos)
15728 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk
15729 #define TSC_IOCCR_G3_IO2_Pos (9U)
15730 #define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos)
15731 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk
15732 #define TSC_IOCCR_G3_IO3_Pos (10U)
15733 #define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos)
15734 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk
15735 #define TSC_IOCCR_G3_IO4_Pos (11U)
15736 #define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos)
15737 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk
15738 #define TSC_IOCCR_G4_IO1_Pos (12U)
15739 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos)
15740 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk
15741 #define TSC_IOCCR_G4_IO2_Pos (13U)
15742 #define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos)
15743 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk
15744 #define TSC_IOCCR_G4_IO3_Pos (14U)
15745 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos)
15746 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk
15747 #define TSC_IOCCR_G4_IO4_Pos (15U)
15748 #define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos)
15749 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk
15750 #define TSC_IOCCR_G5_IO1_Pos (16U)
15751 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos)
15752 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk
15753 #define TSC_IOCCR_G5_IO2_Pos (17U)
15754 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos)
15755 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk
15756 #define TSC_IOCCR_G5_IO3_Pos (18U)
15757 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos)
15758 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk
15759 #define TSC_IOCCR_G5_IO4_Pos (19U)
15760 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos)
15761 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk
15762 #define TSC_IOCCR_G6_IO1_Pos (20U)
15763 #define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos)
15764 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk
15765 #define TSC_IOCCR_G6_IO2_Pos (21U)
15766 #define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos)
15767 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk
15768 #define TSC_IOCCR_G6_IO3_Pos (22U)
15769 #define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos)
15770 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk
15771 #define TSC_IOCCR_G6_IO4_Pos (23U)
15772 #define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos)
15773 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk
15774 #define TSC_IOCCR_G7_IO1_Pos (24U)
15775 #define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos)
15776 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk
15777 #define TSC_IOCCR_G7_IO2_Pos (25U)
15778 #define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos)
15779 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk
15780 #define TSC_IOCCR_G7_IO3_Pos (26U)
15781 #define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos)
15782 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk
15783 #define TSC_IOCCR_G7_IO4_Pos (27U)
15784 #define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos)
15785 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk
15786 #define TSC_IOCCR_G8_IO1_Pos (28U)
15787 #define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos)
15788 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk
15789 #define TSC_IOCCR_G8_IO2_Pos (29U)
15790 #define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos)
15791 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk
15792 #define TSC_IOCCR_G8_IO3_Pos (30U)
15793 #define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos)
15794 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk
15795 #define TSC_IOCCR_G8_IO4_Pos (31U)
15796 #define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos)
15797 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk
15799 /******************* Bit definition for TSC_IOGCSR register *****************/
15800 #define TSC_IOGCSR_G1E_Pos (0U)
15801 #define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos)
15802 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk
15803 #define TSC_IOGCSR_G2E_Pos (1U)
15804 #define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos)
15805 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk
15806 #define TSC_IOGCSR_G3E_Pos (2U)
15807 #define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos)
15808 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk
15809 #define TSC_IOGCSR_G4E_Pos (3U)
15810 #define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos)
15811 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk
15812 #define TSC_IOGCSR_G5E_Pos (4U)
15813 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos)
15814 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk
15815 #define TSC_IOGCSR_G6E_Pos (5U)
15816 #define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos)
15817 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk
15818 #define TSC_IOGCSR_G7E_Pos (6U)
15819 #define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos)
15820 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk
15821 #define TSC_IOGCSR_G8E_Pos (7U)
15822 #define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos)
15823 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk
15824 #define TSC_IOGCSR_G1S_Pos (16U)
15825 #define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos)
15826 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk
15827 #define TSC_IOGCSR_G2S_Pos (17U)
15828 #define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos)
15829 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk
15830 #define TSC_IOGCSR_G3S_Pos (18U)
15831 #define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos)
15832 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk
15833 #define TSC_IOGCSR_G4S_Pos (19U)
15834 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos)
15835 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk
15836 #define TSC_IOGCSR_G5S_Pos (20U)
15837 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos)
15838 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk
15839 #define TSC_IOGCSR_G6S_Pos (21U)
15840 #define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos)
15841 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk
15842 #define TSC_IOGCSR_G7S_Pos (22U)
15843 #define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos)
15844 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk
15845 #define TSC_IOGCSR_G8S_Pos (23U)
15846 #define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos)
15847 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk
15849 /******************* Bit definition for TSC_IOGXCR register *****************/
15850 #define TSC_IOGXCR_CNT_Pos (0U)
15851 #define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos)
15852 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk
15854 /******************************************************************************/
15855 /* */
15856 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
15857 /* */
15858 /******************************************************************************/
15859 /****************** Bit definition for USART_CR1 register *******************/
15860 #define USART_CR1_UE_Pos (0U)
15861 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
15862 #define USART_CR1_UE USART_CR1_UE_Msk
15863 #define USART_CR1_UESM_Pos (1U)
15864 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
15865 #define USART_CR1_UESM USART_CR1_UESM_Msk
15866 #define USART_CR1_RE_Pos (2U)
15867 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
15868 #define USART_CR1_RE USART_CR1_RE_Msk
15869 #define USART_CR1_TE_Pos (3U)
15870 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
15871 #define USART_CR1_TE USART_CR1_TE_Msk
15872 #define USART_CR1_IDLEIE_Pos (4U)
15873 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
15874 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
15875 #define USART_CR1_RXNEIE_Pos (5U)
15876 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
15877 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
15878 #define USART_CR1_TCIE_Pos (6U)
15879 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
15880 #define USART_CR1_TCIE USART_CR1_TCIE_Msk
15881 #define USART_CR1_TXEIE_Pos (7U)
15882 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
15883 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
15884 #define USART_CR1_PEIE_Pos (8U)
15885 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
15886 #define USART_CR1_PEIE USART_CR1_PEIE_Msk
15887 #define USART_CR1_PS_Pos (9U)
15888 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
15889 #define USART_CR1_PS USART_CR1_PS_Msk
15890 #define USART_CR1_PCE_Pos (10U)
15891 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
15892 #define USART_CR1_PCE USART_CR1_PCE_Msk
15893 #define USART_CR1_WAKE_Pos (11U)
15894 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
15895 #define USART_CR1_WAKE USART_CR1_WAKE_Msk
15896 #define USART_CR1_M_Pos (12U)
15897 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
15898 #define USART_CR1_M USART_CR1_M_Msk
15899 #define USART_CR1_M0_Pos (12U)
15900 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
15901 #define USART_CR1_M0 USART_CR1_M0_Msk
15902 #define USART_CR1_MME_Pos (13U)
15903 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
15904 #define USART_CR1_MME USART_CR1_MME_Msk
15905 #define USART_CR1_CMIE_Pos (14U)
15906 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
15907 #define USART_CR1_CMIE USART_CR1_CMIE_Msk
15908 #define USART_CR1_OVER8_Pos (15U)
15909 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
15910 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk
15911 #define USART_CR1_DEDT_Pos (16U)
15912 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
15913 #define USART_CR1_DEDT USART_CR1_DEDT_Msk
15914 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
15915 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
15916 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
15917 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
15918 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
15919 #define USART_CR1_DEAT_Pos (21U)
15920 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
15921 #define USART_CR1_DEAT USART_CR1_DEAT_Msk
15922 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
15923 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
15924 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
15925 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
15926 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
15927 #define USART_CR1_RTOIE_Pos (26U)
15928 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
15929 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
15930 #define USART_CR1_EOBIE_Pos (27U)
15931 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
15932 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
15933 #define USART_CR1_M1_Pos (28U)
15934 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
15935 #define USART_CR1_M1 USART_CR1_M1_Msk
15937 /****************** Bit definition for USART_CR2 register *******************/
15938 #define USART_CR2_ADDM7_Pos (4U)
15939 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
15940 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
15941 #define USART_CR2_LBDL_Pos (5U)
15942 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
15943 #define USART_CR2_LBDL USART_CR2_LBDL_Msk
15944 #define USART_CR2_LBDIE_Pos (6U)
15945 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
15946 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
15947 #define USART_CR2_LBCL_Pos (8U)
15948 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
15949 #define USART_CR2_LBCL USART_CR2_LBCL_Msk
15950 #define USART_CR2_CPHA_Pos (9U)
15951 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
15952 #define USART_CR2_CPHA USART_CR2_CPHA_Msk
15953 #define USART_CR2_CPOL_Pos (10U)
15954 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
15955 #define USART_CR2_CPOL USART_CR2_CPOL_Msk
15956 #define USART_CR2_CLKEN_Pos (11U)
15957 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
15958 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
15959 #define USART_CR2_STOP_Pos (12U)
15960 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
15961 #define USART_CR2_STOP USART_CR2_STOP_Msk
15962 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
15963 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
15964 #define USART_CR2_LINEN_Pos (14U)
15965 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
15966 #define USART_CR2_LINEN USART_CR2_LINEN_Msk
15967 #define USART_CR2_SWAP_Pos (15U)
15968 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
15969 #define USART_CR2_SWAP USART_CR2_SWAP_Msk
15970 #define USART_CR2_RXINV_Pos (16U)
15971 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
15972 #define USART_CR2_RXINV USART_CR2_RXINV_Msk
15973 #define USART_CR2_TXINV_Pos (17U)
15974 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
15975 #define USART_CR2_TXINV USART_CR2_TXINV_Msk
15976 #define USART_CR2_DATAINV_Pos (18U)
15977 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
15978 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
15979 #define USART_CR2_MSBFIRST_Pos (19U)
15980 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
15981 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
15982 #define USART_CR2_ABREN_Pos (20U)
15983 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
15984 #define USART_CR2_ABREN USART_CR2_ABREN_Msk
15985 #define USART_CR2_ABRMODE_Pos (21U)
15986 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
15987 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
15988 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
15989 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
15990 #define USART_CR2_RTOEN_Pos (23U)
15991 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
15992 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
15993 #define USART_CR2_ADD_Pos (24U)
15994 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
15995 #define USART_CR2_ADD USART_CR2_ADD_Msk
15997 /****************** Bit definition for USART_CR3 register *******************/
15998 #define USART_CR3_EIE_Pos (0U)
15999 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
16000 #define USART_CR3_EIE USART_CR3_EIE_Msk
16001 #define USART_CR3_IREN_Pos (1U)
16002 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
16003 #define USART_CR3_IREN USART_CR3_IREN_Msk
16004 #define USART_CR3_IRLP_Pos (2U)
16005 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
16006 #define USART_CR3_IRLP USART_CR3_IRLP_Msk
16007 #define USART_CR3_HDSEL_Pos (3U)
16008 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
16009 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
16010 #define USART_CR3_NACK_Pos (4U)
16011 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
16012 #define USART_CR3_NACK USART_CR3_NACK_Msk
16013 #define USART_CR3_SCEN_Pos (5U)
16014 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
16015 #define USART_CR3_SCEN USART_CR3_SCEN_Msk
16016 #define USART_CR3_DMAR_Pos (6U)
16017 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
16018 #define USART_CR3_DMAR USART_CR3_DMAR_Msk
16019 #define USART_CR3_DMAT_Pos (7U)
16020 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
16021 #define USART_CR3_DMAT USART_CR3_DMAT_Msk
16022 #define USART_CR3_RTSE_Pos (8U)
16023 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
16024 #define USART_CR3_RTSE USART_CR3_RTSE_Msk
16025 #define USART_CR3_CTSE_Pos (9U)
16026 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
16027 #define USART_CR3_CTSE USART_CR3_CTSE_Msk
16028 #define USART_CR3_CTSIE_Pos (10U)
16029 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
16030 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
16031 #define USART_CR3_ONEBIT_Pos (11U)
16032 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
16033 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
16034 #define USART_CR3_OVRDIS_Pos (12U)
16035 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
16036 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
16037 #define USART_CR3_DDRE_Pos (13U)
16038 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
16039 #define USART_CR3_DDRE USART_CR3_DDRE_Msk
16040 #define USART_CR3_DEM_Pos (14U)
16041 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
16042 #define USART_CR3_DEM USART_CR3_DEM_Msk
16043 #define USART_CR3_DEP_Pos (15U)
16044 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
16045 #define USART_CR3_DEP USART_CR3_DEP_Msk
16046 #define USART_CR3_SCARCNT_Pos (17U)
16047 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
16048 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
16049 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
16050 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
16051 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
16052 #define USART_CR3_WUS_Pos (20U)
16053 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
16054 #define USART_CR3_WUS USART_CR3_WUS_Msk
16055 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
16056 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
16057 #define USART_CR3_WUFIE_Pos (22U)
16058 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
16059 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
16060 #define USART_CR3_UCESM_Pos (23U)
16061 #define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos)
16062 #define USART_CR3_UCESM USART_CR3_UCESM_Msk
16064 /****************** Bit definition for USART_BRR register *******************/
16065 #define USART_BRR_DIV_FRACTION_Pos (0U)
16066 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
16067 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
16068 #define USART_BRR_DIV_MANTISSA_Pos (4U)
16069 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
16070 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
16072 /****************** Bit definition for USART_GTPR register ******************/
16073 #define USART_GTPR_PSC_Pos (0U)
16074 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
16075 #define USART_GTPR_PSC USART_GTPR_PSC_Msk
16076 #define USART_GTPR_GT_Pos (8U)
16077 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
16078 #define USART_GTPR_GT USART_GTPR_GT_Msk
16080 /******************* Bit definition for USART_RTOR register *****************/
16081 #define USART_RTOR_RTO_Pos (0U)
16082 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
16083 #define USART_RTOR_RTO USART_RTOR_RTO_Msk
16084 #define USART_RTOR_BLEN_Pos (24U)
16085 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
16086 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
16088 /******************* Bit definition for USART_RQR register ******************/
16089 #define USART_RQR_ABRRQ_Pos (0U)
16090 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
16091 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
16092 #define USART_RQR_SBKRQ_Pos (1U)
16093 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
16094 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
16095 #define USART_RQR_MMRQ_Pos (2U)
16096 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
16097 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
16098 #define USART_RQR_RXFRQ_Pos (3U)
16099 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
16100 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
16101 #define USART_RQR_TXFRQ_Pos (4U)
16102 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
16103 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
16105 /******************* Bit definition for USART_ISR register ******************/
16106 #define USART_ISR_PE_Pos (0U)
16107 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
16108 #define USART_ISR_PE USART_ISR_PE_Msk
16109 #define USART_ISR_FE_Pos (1U)
16110 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
16111 #define USART_ISR_FE USART_ISR_FE_Msk
16112 #define USART_ISR_NE_Pos (2U)
16113 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
16114 #define USART_ISR_NE USART_ISR_NE_Msk
16115 #define USART_ISR_ORE_Pos (3U)
16116 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
16117 #define USART_ISR_ORE USART_ISR_ORE_Msk
16118 #define USART_ISR_IDLE_Pos (4U)
16119 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
16120 #define USART_ISR_IDLE USART_ISR_IDLE_Msk
16121 #define USART_ISR_RXNE_Pos (5U)
16122 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
16123 #define USART_ISR_RXNE USART_ISR_RXNE_Msk
16124 #define USART_ISR_TC_Pos (6U)
16125 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
16126 #define USART_ISR_TC USART_ISR_TC_Msk
16127 #define USART_ISR_TXE_Pos (7U)
16128 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
16129 #define USART_ISR_TXE USART_ISR_TXE_Msk
16130 #define USART_ISR_LBDF_Pos (8U)
16131 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
16132 #define USART_ISR_LBDF USART_ISR_LBDF_Msk
16133 #define USART_ISR_CTSIF_Pos (9U)
16134 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
16135 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
16136 #define USART_ISR_CTS_Pos (10U)
16137 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
16138 #define USART_ISR_CTS USART_ISR_CTS_Msk
16139 #define USART_ISR_RTOF_Pos (11U)
16140 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
16141 #define USART_ISR_RTOF USART_ISR_RTOF_Msk
16142 #define USART_ISR_EOBF_Pos (12U)
16143 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
16144 #define USART_ISR_EOBF USART_ISR_EOBF_Msk
16145 #define USART_ISR_ABRE_Pos (14U)
16146 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
16147 #define USART_ISR_ABRE USART_ISR_ABRE_Msk
16148 #define USART_ISR_ABRF_Pos (15U)
16149 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
16150 #define USART_ISR_ABRF USART_ISR_ABRF_Msk
16151 #define USART_ISR_BUSY_Pos (16U)
16152 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
16153 #define USART_ISR_BUSY USART_ISR_BUSY_Msk
16154 #define USART_ISR_CMF_Pos (17U)
16155 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
16156 #define USART_ISR_CMF USART_ISR_CMF_Msk
16157 #define USART_ISR_SBKF_Pos (18U)
16158 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
16159 #define USART_ISR_SBKF USART_ISR_SBKF_Msk
16160 #define USART_ISR_RWU_Pos (19U)
16161 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
16162 #define USART_ISR_RWU USART_ISR_RWU_Msk
16163 #define USART_ISR_WUF_Pos (20U)
16164 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
16165 #define USART_ISR_WUF USART_ISR_WUF_Msk
16166 #define USART_ISR_TEACK_Pos (21U)
16167 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
16168 #define USART_ISR_TEACK USART_ISR_TEACK_Msk
16169 #define USART_ISR_REACK_Pos (22U)
16170 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
16171 #define USART_ISR_REACK USART_ISR_REACK_Msk
16173 /******************* Bit definition for USART_ICR register ******************/
16174 #define USART_ICR_PECF_Pos (0U)
16175 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
16176 #define USART_ICR_PECF USART_ICR_PECF_Msk
16177 #define USART_ICR_FECF_Pos (1U)
16178 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
16179 #define USART_ICR_FECF USART_ICR_FECF_Msk
16180 #define USART_ICR_NECF_Pos (2U)
16181 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
16182 #define USART_ICR_NECF USART_ICR_NECF_Msk
16183 #define USART_ICR_ORECF_Pos (3U)
16184 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
16185 #define USART_ICR_ORECF USART_ICR_ORECF_Msk
16186 #define USART_ICR_IDLECF_Pos (4U)
16187 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
16188 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
16189 #define USART_ICR_TCCF_Pos (6U)
16190 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
16191 #define USART_ICR_TCCF USART_ICR_TCCF_Msk
16192 #define USART_ICR_LBDCF_Pos (8U)
16193 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
16194 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
16195 #define USART_ICR_CTSCF_Pos (9U)
16196 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
16197 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
16198 #define USART_ICR_RTOCF_Pos (11U)
16199 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
16200 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
16201 #define USART_ICR_EOBCF_Pos (12U)
16202 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
16203 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
16204 #define USART_ICR_CMCF_Pos (17U)
16205 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
16206 #define USART_ICR_CMCF USART_ICR_CMCF_Msk
16207 #define USART_ICR_WUCF_Pos (20U)
16208 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
16209 #define USART_ICR_WUCF USART_ICR_WUCF_Msk
16211 /* Legacy defines */
16212 #define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
16213 #define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
16214 #define USART_ICR_NCF USART_ICR_NECF
16215 
16216 /******************* Bit definition for USART_RDR register ******************/
16217 #define USART_RDR_RDR_Pos (0U)
16218 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
16219 #define USART_RDR_RDR USART_RDR_RDR_Msk
16221 /******************* Bit definition for USART_TDR register ******************/
16222 #define USART_TDR_TDR_Pos (0U)
16223 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
16224 #define USART_TDR_TDR USART_TDR_TDR_Msk
16226 /******************************************************************************/
16227 /* */
16228 /* Single Wire Protocol Master Interface (SWPMI) */
16229 /* */
16230 /******************************************************************************/
16231 
16232 /******************* Bit definition for SWPMI_CR register ********************/
16233 #define SWPMI_CR_RXDMA_Pos (0U)
16234 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
16235 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
16236 #define SWPMI_CR_TXDMA_Pos (1U)
16237 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
16238 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
16239 #define SWPMI_CR_RXMODE_Pos (2U)
16240 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
16241 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
16242 #define SWPMI_CR_TXMODE_Pos (3U)
16243 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
16244 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
16245 #define SWPMI_CR_LPBK_Pos (4U)
16246 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
16247 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
16248 #define SWPMI_CR_SWPACT_Pos (5U)
16249 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
16250 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
16251 #define SWPMI_CR_DEACT_Pos (10U)
16252 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
16253 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
16255 /******************* Bit definition for SWPMI_BRR register ********************/
16256 #define SWPMI_BRR_BR_Pos (0U)
16257 #define SWPMI_BRR_BR_Msk (0x3FUL << SWPMI_BRR_BR_Pos)
16258 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
16260 /******************* Bit definition for SWPMI_ISR register ********************/
16261 #define SWPMI_ISR_RXBFF_Pos (0U)
16262 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
16263 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
16264 #define SWPMI_ISR_TXBEF_Pos (1U)
16265 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
16266 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
16267 #define SWPMI_ISR_RXBERF_Pos (2U)
16268 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
16269 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
16270 #define SWPMI_ISR_RXOVRF_Pos (3U)
16271 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
16272 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
16273 #define SWPMI_ISR_TXUNRF_Pos (4U)
16274 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
16275 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
16276 #define SWPMI_ISR_RXNE_Pos (5U)
16277 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
16278 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
16279 #define SWPMI_ISR_TXE_Pos (6U)
16280 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
16281 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
16282 #define SWPMI_ISR_TCF_Pos (7U)
16283 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
16284 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
16285 #define SWPMI_ISR_SRF_Pos (8U)
16286 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
16287 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
16288 #define SWPMI_ISR_SUSP_Pos (9U)
16289 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
16290 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
16291 #define SWPMI_ISR_DEACTF_Pos (10U)
16292 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
16293 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
16295 /******************* Bit definition for SWPMI_ICR register ********************/
16296 #define SWPMI_ICR_CRXBFF_Pos (0U)
16297 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
16298 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
16299 #define SWPMI_ICR_CTXBEF_Pos (1U)
16300 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
16301 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
16302 #define SWPMI_ICR_CRXBERF_Pos (2U)
16303 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
16304 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
16305 #define SWPMI_ICR_CRXOVRF_Pos (3U)
16306 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
16307 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
16308 #define SWPMI_ICR_CTXUNRF_Pos (4U)
16309 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
16310 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
16311 #define SWPMI_ICR_CTCF_Pos (7U)
16312 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
16313 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
16314 #define SWPMI_ICR_CSRF_Pos (8U)
16315 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
16316 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
16318 /******************* Bit definition for SWPMI_IER register ********************/
16319 #define SWPMI_IER_SRIE_Pos (8U)
16320 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
16321 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
16322 #define SWPMI_IER_TCIE_Pos (7U)
16323 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
16324 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
16325 #define SWPMI_IER_TIE_Pos (6U)
16326 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
16327 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
16328 #define SWPMI_IER_RIE_Pos (5U)
16329 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
16330 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
16331 #define SWPMI_IER_TXUNRIE_Pos (4U)
16332 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
16333 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
16334 #define SWPMI_IER_RXOVRIE_Pos (3U)
16335 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
16336 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
16337 #define SWPMI_IER_RXBERIE_Pos (2U)
16338 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
16339 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
16340 #define SWPMI_IER_TXBEIE_Pos (1U)
16341 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
16342 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
16343 #define SWPMI_IER_RXBFIE_Pos (0U)
16344 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
16345 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
16347 /******************* Bit definition for SWPMI_RFL register ********************/
16348 #define SWPMI_RFL_RFL_Pos (0U)
16349 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
16350 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
16351 #define SWPMI_RFL_RFL_0_1_Pos (0U)
16352 #define SWPMI_RFL_RFL_0_1_Msk (0x3UL << SWPMI_RFL_RFL_0_1_Pos)
16353 #define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk
16355 /******************* Bit definition for SWPMI_TDR register ********************/
16356 #define SWPMI_TDR_TD_Pos (0U)
16357 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
16358 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
16360 /******************* Bit definition for SWPMI_RDR register ********************/
16361 #define SWPMI_RDR_RD_Pos (0U)
16362 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
16363 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
16365 /******************* Bit definition for SWPMI_OR register ********************/
16366 #define SWPMI_OR_TBYP_Pos (0U)
16367 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
16368 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
16369 #define SWPMI_OR_CLASS_Pos (1U)
16370 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
16371 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
16373 /******************************************************************************/
16374 /* */
16375 /* VREFBUF */
16376 /* */
16377 /******************************************************************************/
16378 /******************* Bit definition for VREFBUF_CSR register ****************/
16379 #define VREFBUF_CSR_ENVR_Pos (0U)
16380 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
16381 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
16382 #define VREFBUF_CSR_HIZ_Pos (1U)
16383 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
16384 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
16385 #define VREFBUF_CSR_VRS_Pos (2U)
16386 #define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos)
16387 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
16388 #define VREFBUF_CSR_VRR_Pos (3U)
16389 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
16390 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
16392 /******************* Bit definition for VREFBUF_CCR register ******************/
16393 #define VREFBUF_CCR_TRIM_Pos (0U)
16394 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
16395 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
16397 /******************************************************************************/
16398 /* */
16399 /* Window WATCHDOG */
16400 /* */
16401 /******************************************************************************/
16402 /******************* Bit definition for WWDG_CR register ********************/
16403 #define WWDG_CR_T_Pos (0U)
16404 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
16405 #define WWDG_CR_T WWDG_CR_T_Msk
16406 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
16407 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
16408 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
16409 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
16410 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
16411 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
16412 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
16414 #define WWDG_CR_WDGA_Pos (7U)
16415 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
16416 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
16418 /******************* Bit definition for WWDG_CFR register *******************/
16419 #define WWDG_CFR_W_Pos (0U)
16420 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
16421 #define WWDG_CFR_W WWDG_CFR_W_Msk
16422 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
16423 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
16424 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
16425 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
16426 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
16427 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
16428 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
16430 #define WWDG_CFR_WDGTB_Pos (7U)
16431 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
16432 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
16433 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
16434 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
16436 #define WWDG_CFR_EWI_Pos (9U)
16437 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
16438 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
16440 /******************* Bit definition for WWDG_SR register ********************/
16441 #define WWDG_SR_EWIF_Pos (0U)
16442 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
16443 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
16446 /******************************************************************************/
16447 /* */
16448 /* Debug MCU */
16449 /* */
16450 /******************************************************************************/
16451 /******************** Bit definition for DBGMCU_IDCODE register *************/
16452 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
16453 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
16454 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
16455 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
16456 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
16457 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
16458 
16459 /******************** Bit definition for DBGMCU_CR register *****************/
16460 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
16461 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
16462 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
16463 #define DBGMCU_CR_DBG_STOP_Pos (1U)
16464 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
16465 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
16466 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
16467 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
16468 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
16469 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
16470 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
16471 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
16472 
16473 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
16474 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
16475 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
16476 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
16477 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
16479 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
16480 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
16481 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
16482 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
16483 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
16484 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
16485 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
16486 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
16487 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)
16488 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
16489 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
16490 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
16491 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
16492 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
16493 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
16494 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
16495 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
16496 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
16497 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
16498 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
16499 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)
16500 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
16501 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
16502 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
16503 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
16504 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
16505 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
16506 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
16507 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
16508 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
16509 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
16510 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
16511 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
16512 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
16513 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
16514 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)
16515 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
16516 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
16517 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos)
16518 #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
16519 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
16520 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)
16521 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
16522 
16523 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
16524 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
16525 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
16526 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
16527 
16528 /******************** Bit definition for DBGMCU_APB2FZ register ************/
16529 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
16530 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)
16531 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
16532 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
16533 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)
16534 #define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
16535 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
16536 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)
16537 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
16538 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
16539 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)
16540 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
16541 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
16542 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)
16543 #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
16544 
16545 /******************************************************************************/
16546 /* */
16547 /* USB_OTG */
16548 /* */
16549 /******************************************************************************/
16550 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
16551 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
16552 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
16553 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
16554 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
16555 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
16556 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
16557 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
16558 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
16559 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
16560 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
16561 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
16562 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
16563 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
16564 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
16565 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
16566 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
16567 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
16568 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
16569 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
16570 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
16571 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
16572 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
16573 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
16574 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
16575 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
16576 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
16577 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
16579 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
16580 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
16581 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
16582 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
16583 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
16584 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
16585 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
16586 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
16587 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
16588 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
16589 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
16590 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
16591 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
16592 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
16593 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
16594 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
16595 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
16596 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
16597 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
16599 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
16600 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
16601 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
16602 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
16603 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
16604 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16605 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
16606 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16607 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16608 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16609 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16610 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
16611 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
16612 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
16613 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
16614 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
16615 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
16616 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
16617 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
16618 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
16620 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
16621 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
16622 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
16623 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
16624 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
16625 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
16626 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
16627 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
16628 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
16629 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
16630 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
16631 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
16632 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
16633 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
16634 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
16635 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
16636 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
16637 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
16638 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
16639 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
16640 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
16641 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
16642 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
16643 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
16644 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
16645 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
16646 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
16647 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
16648 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
16649 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
16650 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
16651 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
16652 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
16653 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
16654 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
16655 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
16656 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
16657 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
16658 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
16659 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
16660 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
16661 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
16662 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
16663 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
16664 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
16665 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
16666 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
16667 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
16668 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
16669 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
16670 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
16671 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
16672 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
16673 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
16674 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
16675 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
16676 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
16677 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
16678 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
16679 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
16680 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
16681 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
16683 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
16684 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
16685 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
16686 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
16687 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
16688 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
16689 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
16690 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
16691 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
16692 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
16693 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
16694 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
16695 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
16696 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
16697 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
16698 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
16699 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
16700 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16701 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
16702 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16703 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16704 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16705 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16706 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16707 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
16708 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
16709 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
16710 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
16711 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
16712 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
16714 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
16715 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
16716 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
16717 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
16718 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
16719 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
16720 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
16721 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
16722 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
16723 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
16724 #define USB_OTG_GINTSTS_SOF_Pos (3U)
16725 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
16726 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
16727 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
16728 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
16729 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
16730 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
16731 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
16732 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
16733 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
16734 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
16735 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
16736 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
16737 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
16738 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
16739 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
16740 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
16741 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
16742 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
16743 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
16744 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
16745 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
16746 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
16747 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
16748 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
16749 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
16750 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
16751 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
16752 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
16753 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
16754 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
16755 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
16756 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
16757 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
16758 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
16759 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
16760 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
16761 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
16762 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
16763 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
16764 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
16765 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
16766 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
16767 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
16768 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
16769 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
16770 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
16771 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
16772 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
16773 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
16774 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
16775 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
16776 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
16777 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
16778 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
16779 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
16780 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
16781 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
16782 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
16783 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
16784 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
16785 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
16786 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
16787 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
16788 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
16789 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
16790 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
16791 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
16792 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
16793 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
16794 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
16795 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
16797 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
16798 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
16799 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
16800 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
16801 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
16802 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
16803 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
16804 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
16805 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
16806 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
16807 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
16808 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
16809 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
16810 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
16811 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
16812 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
16813 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
16814 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
16815 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
16816 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
16817 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
16818 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
16819 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
16820 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
16821 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
16822 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
16823 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
16824 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
16825 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
16826 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
16827 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
16828 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
16829 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
16830 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
16831 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
16832 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
16833 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
16834 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
16835 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
16836 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
16837 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
16838 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
16839 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
16840 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
16841 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
16842 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
16843 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
16844 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
16845 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
16846 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
16847 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
16848 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
16849 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
16850 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
16851 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
16852 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
16853 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
16854 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
16855 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
16856 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
16857 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
16858 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
16859 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
16860 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
16861 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
16862 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
16863 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
16864 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
16865 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
16866 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
16867 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
16868 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
16869 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
16870 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
16871 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
16872 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
16873 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
16874 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
16875 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
16876 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
16877 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
16878 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
16880 /******************** Bit definition for USB_OTG_GRXSTSR/GRXSTSP registers ***********/
16881 /* Host mode */
16882 #define USB_OTG_CHNUM_Pos (0U)
16883 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
16884 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
16885 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
16886 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
16887 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
16888 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
16889 /* Device mode */
16890 #define USB_OTG_EPNUM_Pos (0U)
16891 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
16892 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
16893 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
16894 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
16895 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
16896 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
16897 #define USB_OTG_FRMNUM_Pos (21U)
16898 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
16899 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
16900 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
16901 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
16902 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
16903 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
16904 /* Host/Device mode */
16905 #define USB_OTG_BCNT_Pos (4U)
16906 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
16907 #define USB_OTG_BCNT USB_OTG_BCNT_Msk
16908 #define USB_OTG_DPID_Pos (15U)
16909 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
16910 #define USB_OTG_DPID USB_OTG_DPID_Msk
16911 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
16912 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
16913 #define USB_OTG_PKTSTS_Pos (17U)
16914 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
16915 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
16916 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
16917 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
16918 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
16919 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
16921 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
16922 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
16923 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
16924 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
16925 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
16926 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
16927 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
16928 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
16929 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
16930 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
16931 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
16932 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
16933 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
16935 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
16936 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
16937 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
16938 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
16940 /******************** Bit definition for USB_OTG_HNPTXFSIZ/DIEPTXF0 register *********/
16941 #define USB_OTG_NPTXFSA_Pos (0U)
16942 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
16943 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
16944 #define USB_OTG_NPTXFD_Pos (16U)
16945 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
16946 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
16947 #define USB_OTG_TX0FSA_Pos (0U)
16948 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
16949 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
16950 #define USB_OTG_TX0FD_Pos (16U)
16951 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
16952 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
16954 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
16955 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
16956 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
16957 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
16958 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
16959 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16960 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
16961 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16962 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16963 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16964 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16965 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16966 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16967 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16968 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16970 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
16971 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16972 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
16973 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16974 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16975 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16976 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16977 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16978 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16979 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16981 /******************** Bit definition for USB_OTG_GCCFG register ********************/
16982 #define USB_OTG_GCCFG_DCDET_Pos (0U)
16983 #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
16984 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
16985 #define USB_OTG_GCCFG_PDET_Pos (1U)
16986 #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
16987 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
16988 #define USB_OTG_GCCFG_SDET_Pos (2U)
16989 #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
16990 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
16991 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
16992 #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
16993 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
16994 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
16995 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
16996 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
16997 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
16998 #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
16999 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
17000 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
17001 #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
17002 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
17003 #define USB_OTG_GCCFG_PDEN_Pos (19U)
17004 #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
17005 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
17006 #define USB_OTG_GCCFG_SDEN_Pos (20U)
17007 #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
17008 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
17009 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
17010 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
17011 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
17013 /******************** Bit definition for USB_OTG_CID register ********************/
17014 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
17015 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
17016 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
17018 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
17019 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
17020 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
17021 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
17022 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
17023 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
17024 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
17025 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
17026 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
17027 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
17028 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
17029 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
17030 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
17031 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
17032 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
17033 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
17034 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
17035 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
17036 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */
17037 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
17038 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
17039 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
17040 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
17041 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
17042 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
17043 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
17044 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
17045 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
17046 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
17047 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
17048 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
17049 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
17050 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
17051 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
17052 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
17053 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
17054 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
17055 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
17056 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
17057 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
17058 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
17059 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
17060 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
17061 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
17062 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
17063 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
17064 
17065 /* Legacy defines */
17066 #define USB_OTG_GLPMCFG_L1ResumeOK_Pos USB_OTG_GLPMCFG_L1RSMOK_Pos
17067 #define USB_OTG_GLPMCFG_L1ResumeOK_Msk USB_OTG_GLPMCFG_L1RSMOK_Msk
17068 #define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
17069 
17070 /******************** Bit definition for USB_OTG_GPWRDN register **********************/
17071 #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
17072 #define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1UL << USB_OTG_GPWRDN_DISABLEVBUS_Pos)
17073 #define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk
17075 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
17076 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
17077 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
17078 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
17079 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
17080 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
17081 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
17083 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
17084 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
17085 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
17086 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
17087 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
17088 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
17089 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
17091 /******************** Bit definition for USB_OTG_HCFG register ********************/
17092 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
17093 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
17094 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
17095 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
17096 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
17097 #define USB_OTG_HCFG_FSLSS_Pos (2U)
17098 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
17099 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
17101 /******************** Bit definition for USB_OTG_HFIR register ********************/
17102 #define USB_OTG_HFIR_FRIVL_Pos (0U)
17103 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
17104 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
17106 /******************** Bit definition for USB_OTG_HFNUM register ********************/
17107 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
17108 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
17109 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
17110 #define USB_OTG_HFNUM_FTREM_Pos (16U)
17111 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
17112 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
17114 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
17115 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
17116 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
17117 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
17118 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
17119 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17120 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
17121 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17122 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17123 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17124 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17125 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17126 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17127 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17128 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17130 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
17131 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17132 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
17133 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17134 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17135 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17136 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17137 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17138 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17139 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17140 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17142 /******************** Bit definition for USB_OTG_HAINT register ********************/
17143 #define USB_OTG_HAINT_HAINT_Pos (0U)
17144 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
17145 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
17147 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
17148 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
17149 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
17150 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
17152 /******************** Bit definition for USB_OTG_HPRT register ********************/
17153 #define USB_OTG_HPRT_PCSTS_Pos (0U)
17154 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
17155 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
17156 #define USB_OTG_HPRT_PCDET_Pos (1U)
17157 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
17158 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
17159 #define USB_OTG_HPRT_PENA_Pos (2U)
17160 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
17161 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
17162 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
17163 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
17164 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
17165 #define USB_OTG_HPRT_POCA_Pos (4U)
17166 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
17167 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
17168 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
17169 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
17170 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
17171 #define USB_OTG_HPRT_PRES_Pos (6U)
17172 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
17173 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
17174 #define USB_OTG_HPRT_PSUSP_Pos (7U)
17175 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
17176 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
17177 #define USB_OTG_HPRT_PRST_Pos (8U)
17178 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
17179 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
17181 #define USB_OTG_HPRT_PLSTS_Pos (10U)
17182 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
17183 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
17184 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
17185 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
17186 #define USB_OTG_HPRT_PPWR_Pos (12U)
17187 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
17188 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
17190 #define USB_OTG_HPRT_PTCTL_Pos (13U)
17191 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
17192 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
17193 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
17194 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
17195 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
17196 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
17198 #define USB_OTG_HPRT_PSPD_Pos (17U)
17199 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
17200 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
17201 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
17202 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
17204 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
17205 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
17206 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
17207 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
17209 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
17210 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
17211 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
17212 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
17213 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
17214 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
17215 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
17216 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
17217 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
17218 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
17219 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
17220 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
17221 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
17223 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
17224 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
17225 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
17226 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
17227 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
17229 #define USB_OTG_HCCHAR_MC_Pos (20U)
17230 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
17231 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
17232 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
17233 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
17235 #define USB_OTG_HCCHAR_DAD_Pos (22U)
17236 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
17237 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
17238 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
17239 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
17240 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
17241 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
17242 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
17243 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
17244 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
17245 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
17246 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
17247 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
17248 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
17249 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
17250 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
17251 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
17252 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
17253 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
17255 /******************** Bit definition for USB_OTG_HCINT register ********************/
17256 #define USB_OTG_HCINT_XFRC_Pos (0U)
17257 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
17258 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
17259 #define USB_OTG_HCINT_CHH_Pos (1U)
17260 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
17261 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
17262 #define USB_OTG_HCINT_AHBERR_Pos (2U)
17263 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
17264 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
17265 #define USB_OTG_HCINT_STALL_Pos (3U)
17266 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
17267 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
17268 #define USB_OTG_HCINT_NAK_Pos (4U)
17269 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
17270 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
17271 #define USB_OTG_HCINT_ACK_Pos (5U)
17272 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
17273 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
17274 #define USB_OTG_HCINT_NYET_Pos (6U)
17275 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
17276 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
17277 #define USB_OTG_HCINT_TXERR_Pos (7U)
17278 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
17279 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
17280 #define USB_OTG_HCINT_BBERR_Pos (8U)
17281 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
17282 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
17283 #define USB_OTG_HCINT_FRMOR_Pos (9U)
17284 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
17285 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
17286 #define USB_OTG_HCINT_DTERR_Pos (10U)
17287 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
17288 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
17290 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
17291 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
17292 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
17293 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
17294 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
17295 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
17296 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
17297 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
17298 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
17299 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
17300 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
17301 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
17302 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
17303 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
17304 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
17305 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
17306 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
17307 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
17308 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
17309 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
17310 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
17311 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
17312 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
17313 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
17314 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
17315 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
17316 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
17317 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
17318 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
17319 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
17320 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
17321 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
17322 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
17323 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
17325 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
17326 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
17327 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
17328 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
17329 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
17330 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
17331 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
17332 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
17333 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
17334 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
17335 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
17336 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
17337 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
17338 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
17339 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
17341 /******************** Bit definition for USB_OTG_HCDMA register *********************/
17342 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
17343 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
17344 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
17346 /******************** Bit definition for USB_OTG_DCFG register ********************/
17347 #define USB_OTG_DCFG_DSPD_Pos (0U)
17348 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
17349 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
17350 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
17351 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
17352 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
17353 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
17354 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
17355 #define USB_OTG_DCFG_DAD_Pos (4U)
17356 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
17357 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
17358 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
17359 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
17360 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
17361 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
17362 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
17363 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
17364 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
17365 #define USB_OTG_DCFG_PFIVL_Pos (11U)
17366 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
17367 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
17368 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
17369 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
17370 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
17371 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
17372 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
17373 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
17374 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
17376 /******************** Bit definition for USB_OTG_DCTL register ********************/
17377 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
17378 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
17379 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
17380 #define USB_OTG_DCTL_SDIS_Pos (1U)
17381 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
17382 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
17383 #define USB_OTG_DCTL_GINSTS_Pos (2U)
17384 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
17385 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
17386 #define USB_OTG_DCTL_GONSTS_Pos (3U)
17387 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
17388 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
17389 #define USB_OTG_DCTL_TCTL_Pos (4U)
17390 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
17391 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
17392 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
17393 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
17394 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
17395 #define USB_OTG_DCTL_SGINAK_Pos (7U)
17396 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
17397 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
17398 #define USB_OTG_DCTL_CGINAK_Pos (8U)
17399 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
17400 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
17401 #define USB_OTG_DCTL_SGONAK_Pos (9U)
17402 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
17403 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
17404 #define USB_OTG_DCTL_CGONAK_Pos (10U)
17405 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
17406 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
17407 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
17408 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
17409 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
17411 /******************** Bit definition for USB_OTG_DSTS register ********************/
17412 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
17413 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
17414 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
17415 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
17416 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
17417 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
17418 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
17419 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
17420 #define USB_OTG_DSTS_EERR_Pos (3U)
17421 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
17422 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
17423 #define USB_OTG_DSTS_FNSOF_Pos (8U)
17424 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
17425 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
17427 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
17428 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
17429 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
17430 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
17431 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
17432 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
17433 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
17434 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
17435 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
17436 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
17437 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
17438 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
17439 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
17440 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
17441 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
17442 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
17443 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
17444 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
17445 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
17446 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
17447 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
17448 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
17449 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
17450 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
17451 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
17453 /* Legacy defines */
17454 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos USB_OTG_DIEPMSK_XFRCM_Pos
17455 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk USB_OTG_DIEPMSK_XFRCM_Msk
17456 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPMSK_XFRCM
17457 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos USB_OTG_DIEPMSK_EPDM_Pos
17458 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk USB_OTG_DIEPMSK_EPDM_Msk
17459 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPMSK_EPDM
17460 #define USB_OTG_DIEPEACHMSK1_TOM_Pos USB_OTG_DIEPMSK_TOM_Pos
17461 #define USB_OTG_DIEPEACHMSK1_TOM_Msk USB_OTG_DIEPMSK_TOM_Msk
17462 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPMSK_TOM
17463 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos USB_OTG_DIEPMSK_ITTXFEMSK_Pos
17464 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk USB_OTG_DIEPMSK_ITTXFEMSK_Msk
17465 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK
17466 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos USB_OTG_DIEPMSK_INEPNMM_Pos
17467 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk USB_OTG_DIEPMSK_INEPNMM_Msk
17468 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPMSK_INEPNMM
17469 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos USB_OTG_DIEPMSK_INEPNEM_Pos
17470 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk USB_OTG_DIEPMSK_INEPNEM_Pos
17471 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPMSK_INEPNEM
17472 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos USB_OTG_DIEPMSK_TXFURM_Pos
17473 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk USB_OTG_DIEPMSK_TXFURM_Msk
17474 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPMSK_TXFURM
17475 #define USB_OTG_DIEPEACHMSK1_BIM_Pos USB_OTG_DIEPMSK_BIM_Pos
17476 #define USB_OTG_DIEPEACHMSK1_BIM_Msk USB_OTG_DIEPMSK_BIM_Msk
17477 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPMSK_BIM
17478 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
17479 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
17480 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
17482 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
17483 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
17484 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
17485 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
17486 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
17487 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
17488 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
17489 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
17490 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
17491 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
17492 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
17493 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
17494 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
17495 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
17496 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
17497 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
17498 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
17499 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
17500 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
17501 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
17502 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
17503 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
17505 /* Legacy defines */
17506 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos USB_OTG_DOEPMSK_XFRCM_Pos
17507 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk USB_OTG_DOEPMSK_XFRCM_Msk
17508 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPMSK_XFRCM
17509 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos USB_OTG_DOEPMSK_EPDM_Pos
17510 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk USB_OTG_DOEPMSK_EPDM_Msk
17511 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPMSK_EPDM
17512 #define USB_OTG_DOEPEACHMSK1_TOM_Pos USB_OTG_DOEPMSK_STUPM_Pos
17513 #define USB_OTG_DOEPEACHMSK1_TOM_Msk USB_OTG_DOEPMSK_STUPM_Msk
17514 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPMSK_STUPM
17515 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos USB_OTG_DOEPMSK_OTEPDM_Pos
17516 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk USB_OTG_DOEPMSK_OTEPDM_Msk
17517 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPMSK_OTEPDM
17518 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
17519 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
17520 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
17521 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos USB_OTG_DOEPMSK_B2BSTUP_Pos
17522 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk USB_OTG_DOEPMSK_B2BSTUP_Msk
17523 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPMSK_B2BSTUP
17524 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos USB_OTG_DOEPMSK_OPEM_Pos
17525 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk USB_OTG_DOEPMSK_OPEM_Msk
17526 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPMSK_OPEM
17527 #define USB_OTG_DOEPEACHMSK1_BIM_Pos USB_OTG_DOEPMSK_BOIM_Pos
17528 #define USB_OTG_DOEPEACHMSK1_BIM_Msk USB_OTG_DOEPMSK_BOIM_Msk
17529 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPMSK_BOIM
17530 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
17531 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
17532 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
17533 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
17534 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
17535 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
17536 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
17537 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
17538 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
17540 /******************** Bit definition for USB_OTG_DAINT register ********************/
17541 #define USB_OTG_DAINT_IEPINT_Pos (0U)
17542 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
17543 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
17544 #define USB_OTG_DAINT_OEPINT_Pos (16U)
17545 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
17546 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
17548 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
17549 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
17550 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
17551 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
17552 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
17553 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
17554 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
17556 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
17557 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
17558 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
17559 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
17561 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
17562 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
17563 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
17564 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
17566 /******************** Bit definition for USB_OTG_DTHRCTL register ***************/
17567 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
17568 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
17569 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
17570 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
17571 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
17572 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
17573 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
17574 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17575 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
17576 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17577 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17578 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17579 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17580 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17581 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17582 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17583 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17584 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17585 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
17586 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
17587 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
17588 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
17589 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17590 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
17591 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17592 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17593 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17594 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17595 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17596 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17597 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17598 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17599 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17600 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
17601 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
17602 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
17604 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
17605 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
17606 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
17607 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
17609 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
17610 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
17611 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
17612 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
17613 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
17614 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
17615 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
17617 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
17618 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
17619 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
17620 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
17621 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
17622 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
17623 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
17625 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
17626 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
17627 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
17628 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
17629 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
17630 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
17631 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
17632 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
17633 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
17634 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
17635 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
17636 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
17637 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
17638 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
17639 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17640 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
17641 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17642 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17643 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
17644 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
17645 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
17646 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
17647 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17648 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
17649 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17650 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17651 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17652 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17653 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
17654 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
17655 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
17656 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
17657 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
17658 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
17659 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
17660 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
17661 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
17662 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
17663 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
17664 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
17665 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
17666 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
17667 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
17668 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
17669 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
17670 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
17672 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
17673 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
17674 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
17675 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
17676 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
17677 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
17678 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
17679 #define USB_OTG_DIEPINT_TOC_Pos (3U)
17680 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
17681 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
17682 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
17683 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
17684 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
17685 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
17686 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
17687 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
17688 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
17689 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
17690 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
17691 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
17692 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
17693 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
17694 #define USB_OTG_DIEPINT_BNA_Pos (9U)
17695 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
17696 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
17697 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
17698 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
17699 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
17700 #define USB_OTG_DIEPINT_BERR_Pos (12U)
17701 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
17702 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
17703 #define USB_OTG_DIEPINT_NAK_Pos (13U)
17704 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
17705 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
17707 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
17708 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
17709 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
17710 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
17711 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
17712 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
17713 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
17714 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
17715 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
17716 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
17718 /******************** Bit definition for USB_OTG_DIEPDMA register *********************/
17719 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
17720 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
17721 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
17723 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
17724 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
17725 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
17726 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
17728 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
17729 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
17730 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
17731 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
17732 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
17733 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
17734 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
17735 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
17736 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
17737 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
17738 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
17739 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
17740 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
17741 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
17742 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
17743 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
17744 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
17745 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
17746 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
17747 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
17748 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
17749 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
17750 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
17751 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
17752 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
17753 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
17754 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
17755 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
17756 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
17757 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
17758 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
17759 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
17760 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
17761 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
17762 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
17763 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
17764 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
17765 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
17766 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
17768 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
17769 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
17770 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
17771 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
17772 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
17773 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
17774 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
17775 #define USB_OTG_DOEPINT_STUP_Pos (3U)
17776 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
17777 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
17778 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
17779 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
17780 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
17781 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
17782 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
17783 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
17784 #define USB_OTG_DOEPINT_NYET_Pos (14U)
17785 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
17786 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
17788 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
17789 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
17790 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
17791 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
17792 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
17793 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
17794 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
17795 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
17796 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
17797 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
17798 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
17799 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
17801 /******************** Bit definition for USB_OTG_PCGCCTL register ********************/
17802 #define USB_OTG_PCGCCTL_STPPCLK_Pos (0U)
17803 #define USB_OTG_PCGCCTL_STPPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STPPCLK_Pos)
17804 #define USB_OTG_PCGCCTL_STPPCLK USB_OTG_PCGCCTL_STPPCLK_Msk
17805 #define USB_OTG_PCGCCTL_GATEHCLK_Pos (1U)
17806 #define USB_OTG_PCGCCTL_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATEHCLK_Pos)
17807 #define USB_OTG_PCGCCTL_GATEHCLK USB_OTG_PCGCCTL_GATEHCLK_Msk
17808 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
17809 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
17810 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
17812 /* Legacy defines */
17813 #define USB_OTG_PCGCCTL_STOPCLK_Pos USB_OTG_PCGCCTL_STPPCLK_Pos
17814 #define USB_OTG_PCGCCTL_STOPCLK_Msk USB_OTG_PCGCCTL_STPPCLK_Msk
17815 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
17816 #define USB_OTG_PCGCCTL_GATECLK_Pos USB_OTG_PCGCCTL_GATEHCLK_Pos
17817 #define USB_OTG_PCGCCTL_GATECLK_Msk USB_OTG_PCGCCTL_GATEHCLK_Msk
17818 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
17819 #define USB_OTG_PCGCR_STPPCLK_Pos USB_OTG_PCGCCTL_STPPCLK_Pos
17820 #define USB_OTG_PCGCR_STPPCLK_Msk USB_OTG_PCGCCTL_STPPCLK_Msk
17821 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCCTL_STPPCLK
17822 #define USB_OTG_PCGCR_GATEHCLK_Pos USB_OTG_PCGCCTL_GATEHCLK_Pos
17823 #define USB_OTG_PCGCR_GATEHCLK_Msk USB_OTG_PCGCCTL_GATEHCLK_Msk
17824 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCCTL_GATEHCLK
17825 #define USB_OTG_PCGCR_PHYSUSP_Pos USB_OTG_PCGCCTL_PHYSUSP_Pos
17826 #define USB_OTG_PCGCR_PHYSUSP_Msk USB_OTG_PCGCCTL_PHYSUSP_Msk
17827 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP
17828 #define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
17829 #define USB_OTG_GHWCFG3_LPMMode_Msk (0x1UL << USB_OTG_GHWCFG3_LPMMode_Pos)
17830 #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
17831 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
17832 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
17833 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
17834 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17835 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17836 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17837 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17838 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17839 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17840 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17841 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
17842 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
17843 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
17844 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17845 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17846 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17847 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17848 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17849 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17850 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17851 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
17852 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
17853 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
17854 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
17855 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
17856 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
17857 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
17858 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
17859 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
17860 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
17861 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
17876 /******************************* ADC Instances ********************************/
17877 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17878  ((INSTANCE) == ADC2) || \
17879  ((INSTANCE) == ADC3))
17880 
17881 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
17882 
17883 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
17884 
17885 /******************************** CAN Instances ******************************/
17886 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
17887 
17888 /******************************** COMP Instances ******************************/
17889 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
17890  ((INSTANCE) == COMP2))
17891 
17892 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
17893 
17894 /******************** COMP Instances with window mode capability **************/
17895 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
17896 
17897 /******************************* CRC Instances ********************************/
17898 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
17899 
17900 /******************************* DAC Instances ********************************/
17901 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
17902 
17903 /****************************** DFSDM Instances *******************************/
17904 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
17905  ((INSTANCE) == DFSDM1_Filter1) || \
17906  ((INSTANCE) == DFSDM1_Filter2) || \
17907  ((INSTANCE) == DFSDM1_Filter3))
17908 
17909 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
17910  ((INSTANCE) == DFSDM1_Channel1) || \
17911  ((INSTANCE) == DFSDM1_Channel2) || \
17912  ((INSTANCE) == DFSDM1_Channel3) || \
17913  ((INSTANCE) == DFSDM1_Channel4) || \
17914  ((INSTANCE) == DFSDM1_Channel5) || \
17915  ((INSTANCE) == DFSDM1_Channel6) || \
17916  ((INSTANCE) == DFSDM1_Channel7))
17917 
17918 /******************************** DMA Instances *******************************/
17919 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
17920  ((INSTANCE) == DMA1_Channel2) || \
17921  ((INSTANCE) == DMA1_Channel3) || \
17922  ((INSTANCE) == DMA1_Channel4) || \
17923  ((INSTANCE) == DMA1_Channel5) || \
17924  ((INSTANCE) == DMA1_Channel6) || \
17925  ((INSTANCE) == DMA1_Channel7) || \
17926  ((INSTANCE) == DMA2_Channel1) || \
17927  ((INSTANCE) == DMA2_Channel2) || \
17928  ((INSTANCE) == DMA2_Channel3) || \
17929  ((INSTANCE) == DMA2_Channel4) || \
17930  ((INSTANCE) == DMA2_Channel5) || \
17931  ((INSTANCE) == DMA2_Channel6) || \
17932  ((INSTANCE) == DMA2_Channel7))
17933 
17934 /******************************* GPIO Instances *******************************/
17935 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
17936  ((INSTANCE) == GPIOB) || \
17937  ((INSTANCE) == GPIOC) || \
17938  ((INSTANCE) == GPIOD) || \
17939  ((INSTANCE) == GPIOE) || \
17940  ((INSTANCE) == GPIOF) || \
17941  ((INSTANCE) == GPIOG) || \
17942  ((INSTANCE) == GPIOH))
17943 
17944 /******************************* GPIO AF Instances ****************************/
17945 /* On L4, all GPIO Bank support AF */
17946 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17947 
17948 /**************************** GPIO Lock Instances *****************************/
17949 /* On L4, all GPIO Bank support the Lock mechanism */
17950 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17951 
17952 /******************************** I2C Instances *******************************/
17953 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17954  ((INSTANCE) == I2C2) || \
17955  ((INSTANCE) == I2C3))
17956 
17957 /****************** I2C Instances : wakeup capability from stop modes *********/
17958 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
17959 
17960 /******************************* LCD Instances ********************************/
17961 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
17962 
17963 /******************************* HCD Instances *******************************/
17964 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
17965 
17966 /****************************** OPAMP Instances *******************************/
17967 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
17968  ((INSTANCE) == OPAMP2))
17969 
17970 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
17971 
17972 /******************************* PCD Instances *******************************/
17973 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
17974 
17975 /******************************* QSPI Instances *******************************/
17976 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
17977 
17978 /******************************* RNG Instances ********************************/
17979 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
17980 
17981 /****************************** RTC Instances *********************************/
17982 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
17983 
17984 /******************************** SAI Instances *******************************/
17985 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
17986  ((INSTANCE) == SAI1_Block_B) || \
17987  ((INSTANCE) == SAI2_Block_A) || \
17988  ((INSTANCE) == SAI2_Block_B))
17989 
17990 /****************************** SDMMC Instances *******************************/
17991 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
17992 
17993 /****************************** SMBUS Instances *******************************/
17994 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17995  ((INSTANCE) == I2C2) || \
17996  ((INSTANCE) == I2C3))
17997 
17998 /******************************** SPI Instances *******************************/
17999 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
18000  ((INSTANCE) == SPI2) || \
18001  ((INSTANCE) == SPI3))
18002 
18003 /******************************** SWPMI Instances *****************************/
18004 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
18005 
18006 /****************** LPTIM Instances : All supported instances *****************/
18007 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
18008  ((INSTANCE) == LPTIM2))
18009 
18010 /****************** TIM Instances : All supported instances *******************/
18011 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18012  ((INSTANCE) == TIM2) || \
18013  ((INSTANCE) == TIM3) || \
18014  ((INSTANCE) == TIM4) || \
18015  ((INSTANCE) == TIM5) || \
18016  ((INSTANCE) == TIM6) || \
18017  ((INSTANCE) == TIM7) || \
18018  ((INSTANCE) == TIM8) || \
18019  ((INSTANCE) == TIM15) || \
18020  ((INSTANCE) == TIM16) || \
18021  ((INSTANCE) == TIM17))
18022 
18023 /****************** TIM Instances : supporting 32 bits counter ****************/
18024 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
18025  ((INSTANCE) == TIM5))
18026 
18027 /****************** TIM Instances : supporting the break function *************/
18028 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18029  ((INSTANCE) == TIM8) || \
18030  ((INSTANCE) == TIM15) || \
18031  ((INSTANCE) == TIM16) || \
18032  ((INSTANCE) == TIM17))
18033 
18034 /************** TIM Instances : supporting Break source selection *************/
18035 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18036  ((INSTANCE) == TIM8) || \
18037  ((INSTANCE) == TIM15) || \
18038  ((INSTANCE) == TIM16) || \
18039  ((INSTANCE) == TIM17))
18040 
18041 /****************** TIM Instances : supporting 2 break inputs *****************/
18042 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18043  ((INSTANCE) == TIM8))
18044 
18045 /************* TIM Instances : at least 1 capture/compare channel *************/
18046 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18047  ((INSTANCE) == TIM2) || \
18048  ((INSTANCE) == TIM3) || \
18049  ((INSTANCE) == TIM4) || \
18050  ((INSTANCE) == TIM5) || \
18051  ((INSTANCE) == TIM8) || \
18052  ((INSTANCE) == TIM15) || \
18053  ((INSTANCE) == TIM16) || \
18054  ((INSTANCE) == TIM17))
18055 
18056 /************ TIM Instances : at least 2 capture/compare channels *************/
18057 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18058  ((INSTANCE) == TIM2) || \
18059  ((INSTANCE) == TIM3) || \
18060  ((INSTANCE) == TIM4) || \
18061  ((INSTANCE) == TIM5) || \
18062  ((INSTANCE) == TIM8) || \
18063  ((INSTANCE) == TIM15))
18064 
18065 /************ TIM Instances : at least 3 capture/compare channels *************/
18066 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18067  ((INSTANCE) == TIM2) || \
18068  ((INSTANCE) == TIM3) || \
18069  ((INSTANCE) == TIM4) || \
18070  ((INSTANCE) == TIM5) || \
18071  ((INSTANCE) == TIM8))
18072 
18073 /************ TIM Instances : at least 4 capture/compare channels *************/
18074 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18075  ((INSTANCE) == TIM2) || \
18076  ((INSTANCE) == TIM3) || \
18077  ((INSTANCE) == TIM4) || \
18078  ((INSTANCE) == TIM5) || \
18079  ((INSTANCE) == TIM8))
18080 
18081 /****************** TIM Instances : at least 5 capture/compare channels *******/
18082 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18083  ((INSTANCE) == TIM8))
18084 
18085 /****************** TIM Instances : at least 6 capture/compare channels *******/
18086 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18087  ((INSTANCE) == TIM8))
18088 
18089 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
18090 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18091  ((INSTANCE) == TIM8) || \
18092  ((INSTANCE) == TIM15) || \
18093  ((INSTANCE) == TIM16) || \
18094  ((INSTANCE) == TIM17))
18095 
18096 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
18097 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18098  ((INSTANCE) == TIM2) || \
18099  ((INSTANCE) == TIM3) || \
18100  ((INSTANCE) == TIM4) || \
18101  ((INSTANCE) == TIM5) || \
18102  ((INSTANCE) == TIM6) || \
18103  ((INSTANCE) == TIM7) || \
18104  ((INSTANCE) == TIM8) || \
18105  ((INSTANCE) == TIM15) || \
18106  ((INSTANCE) == TIM16) || \
18107  ((INSTANCE) == TIM17))
18108 
18109 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
18110 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18111  ((INSTANCE) == TIM2) || \
18112  ((INSTANCE) == TIM3) || \
18113  ((INSTANCE) == TIM4) || \
18114  ((INSTANCE) == TIM5) || \
18115  ((INSTANCE) == TIM8) || \
18116  ((INSTANCE) == TIM15) || \
18117  ((INSTANCE) == TIM16) || \
18118  ((INSTANCE) == TIM17))
18119 
18120 /******************** TIM Instances : DMA burst feature ***********************/
18121 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18122  ((INSTANCE) == TIM2) || \
18123  ((INSTANCE) == TIM3) || \
18124  ((INSTANCE) == TIM4) || \
18125  ((INSTANCE) == TIM5) || \
18126  ((INSTANCE) == TIM8) || \
18127  ((INSTANCE) == TIM15) || \
18128  ((INSTANCE) == TIM16) || \
18129  ((INSTANCE) == TIM17))
18130 
18131 /******************* TIM Instances : output(s) available **********************/
18132 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
18133  ((((INSTANCE) == TIM1) && \
18134  (((CHANNEL) == TIM_CHANNEL_1) || \
18135  ((CHANNEL) == TIM_CHANNEL_2) || \
18136  ((CHANNEL) == TIM_CHANNEL_3) || \
18137  ((CHANNEL) == TIM_CHANNEL_4) || \
18138  ((CHANNEL) == TIM_CHANNEL_5) || \
18139  ((CHANNEL) == TIM_CHANNEL_6))) \
18140  || \
18141  (((INSTANCE) == TIM2) && \
18142  (((CHANNEL) == TIM_CHANNEL_1) || \
18143  ((CHANNEL) == TIM_CHANNEL_2) || \
18144  ((CHANNEL) == TIM_CHANNEL_3) || \
18145  ((CHANNEL) == TIM_CHANNEL_4))) \
18146  || \
18147  (((INSTANCE) == TIM3) && \
18148  (((CHANNEL) == TIM_CHANNEL_1) || \
18149  ((CHANNEL) == TIM_CHANNEL_2) || \
18150  ((CHANNEL) == TIM_CHANNEL_3) || \
18151  ((CHANNEL) == TIM_CHANNEL_4))) \
18152  || \
18153  (((INSTANCE) == TIM4) && \
18154  (((CHANNEL) == TIM_CHANNEL_1) || \
18155  ((CHANNEL) == TIM_CHANNEL_2) || \
18156  ((CHANNEL) == TIM_CHANNEL_3) || \
18157  ((CHANNEL) == TIM_CHANNEL_4))) \
18158  || \
18159  (((INSTANCE) == TIM5) && \
18160  (((CHANNEL) == TIM_CHANNEL_1) || \
18161  ((CHANNEL) == TIM_CHANNEL_2) || \
18162  ((CHANNEL) == TIM_CHANNEL_3) || \
18163  ((CHANNEL) == TIM_CHANNEL_4))) \
18164  || \
18165  (((INSTANCE) == TIM8) && \
18166  (((CHANNEL) == TIM_CHANNEL_1) || \
18167  ((CHANNEL) == TIM_CHANNEL_2) || \
18168  ((CHANNEL) == TIM_CHANNEL_3) || \
18169  ((CHANNEL) == TIM_CHANNEL_4) || \
18170  ((CHANNEL) == TIM_CHANNEL_5) || \
18171  ((CHANNEL) == TIM_CHANNEL_6))) \
18172  || \
18173  (((INSTANCE) == TIM15) && \
18174  (((CHANNEL) == TIM_CHANNEL_1) || \
18175  ((CHANNEL) == TIM_CHANNEL_2))) \
18176  || \
18177  (((INSTANCE) == TIM16) && \
18178  (((CHANNEL) == TIM_CHANNEL_1))) \
18179  || \
18180  (((INSTANCE) == TIM17) && \
18181  (((CHANNEL) == TIM_CHANNEL_1))))
18182 
18183 /****************** TIM Instances : supporting complementary output(s) ********/
18184 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
18185  ((((INSTANCE) == TIM1) && \
18186  (((CHANNEL) == TIM_CHANNEL_1) || \
18187  ((CHANNEL) == TIM_CHANNEL_2) || \
18188  ((CHANNEL) == TIM_CHANNEL_3))) \
18189  || \
18190  (((INSTANCE) == TIM8) && \
18191  (((CHANNEL) == TIM_CHANNEL_1) || \
18192  ((CHANNEL) == TIM_CHANNEL_2) || \
18193  ((CHANNEL) == TIM_CHANNEL_3))) \
18194  || \
18195  (((INSTANCE) == TIM15) && \
18196  ((CHANNEL) == TIM_CHANNEL_1)) \
18197  || \
18198  (((INSTANCE) == TIM16) && \
18199  ((CHANNEL) == TIM_CHANNEL_1)) \
18200  || \
18201  (((INSTANCE) == TIM17) && \
18202  ((CHANNEL) == TIM_CHANNEL_1)))
18203 
18204 /****************** TIM Instances : supporting clock division *****************/
18205 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18206  ((INSTANCE) == TIM2) || \
18207  ((INSTANCE) == TIM3) || \
18208  ((INSTANCE) == TIM4) || \
18209  ((INSTANCE) == TIM5) || \
18210  ((INSTANCE) == TIM8) || \
18211  ((INSTANCE) == TIM15) || \
18212  ((INSTANCE) == TIM16) || \
18213  ((INSTANCE) == TIM17))
18214 
18215 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
18216 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18217  ((INSTANCE) == TIM2) || \
18218  ((INSTANCE) == TIM3) || \
18219  ((INSTANCE) == TIM4) || \
18220  ((INSTANCE) == TIM5) || \
18221  ((INSTANCE) == TIM8) || \
18222  ((INSTANCE) == TIM15))
18223 
18224 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
18225 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18226  ((INSTANCE) == TIM2) || \
18227  ((INSTANCE) == TIM3) || \
18228  ((INSTANCE) == TIM4) || \
18229  ((INSTANCE) == TIM5) || \
18230  ((INSTANCE) == TIM8))
18231 
18232 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
18233 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18234  ((INSTANCE) == TIM2) || \
18235  ((INSTANCE) == TIM3) || \
18236  ((INSTANCE) == TIM4) || \
18237  ((INSTANCE) == TIM5) || \
18238  ((INSTANCE) == TIM8) || \
18239  ((INSTANCE) == TIM15))
18240 
18241 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
18242 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18243  ((INSTANCE) == TIM2) || \
18244  ((INSTANCE) == TIM3) || \
18245  ((INSTANCE) == TIM4) || \
18246  ((INSTANCE) == TIM5) || \
18247  ((INSTANCE) == TIM8) || \
18248  ((INSTANCE) == TIM15))
18249 
18250 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
18251 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18252  ((INSTANCE) == TIM8))
18253 
18254 /****************** TIM Instances : supporting commutation event generation ***/
18255 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18256  ((INSTANCE) == TIM8) || \
18257  ((INSTANCE) == TIM15) || \
18258  ((INSTANCE) == TIM16) || \
18259  ((INSTANCE) == TIM17))
18260 
18261 /****************** TIM Instances : supporting counting mode selection ********/
18262 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18263  ((INSTANCE) == TIM2) || \
18264  ((INSTANCE) == TIM3) || \
18265  ((INSTANCE) == TIM4) || \
18266  ((INSTANCE) == TIM5) || \
18267  ((INSTANCE) == TIM8))
18268 
18269 /****************** TIM Instances : supporting encoder interface **************/
18270 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18271  ((INSTANCE) == TIM2) || \
18272  ((INSTANCE) == TIM3) || \
18273  ((INSTANCE) == TIM4) || \
18274  ((INSTANCE) == TIM5) || \
18275  ((INSTANCE) == TIM8))
18276 
18277 /****************** TIM Instances : supporting Hall sensor interface **********/
18278 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18279  ((INSTANCE) == TIM2) || \
18280  ((INSTANCE) == TIM3) || \
18281  ((INSTANCE) == TIM4) || \
18282  ((INSTANCE) == TIM5) || \
18283  ((INSTANCE) == TIM8))
18284 
18285 /**************** TIM Instances : external trigger input available ************/
18286 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18287  ((INSTANCE) == TIM2) || \
18288  ((INSTANCE) == TIM3) || \
18289  ((INSTANCE) == TIM4) || \
18290  ((INSTANCE) == TIM5) || \
18291  ((INSTANCE) == TIM8))
18292 
18293 /************* TIM Instances : supporting ETR source selection ***************/
18294 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18295  ((INSTANCE) == TIM2) || \
18296  ((INSTANCE) == TIM3) || \
18297  ((INSTANCE) == TIM8))
18298 
18299 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
18300 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18301  ((INSTANCE) == TIM2) || \
18302  ((INSTANCE) == TIM3) || \
18303  ((INSTANCE) == TIM4) || \
18304  ((INSTANCE) == TIM5) || \
18305  ((INSTANCE) == TIM6) || \
18306  ((INSTANCE) == TIM7) || \
18307  ((INSTANCE) == TIM8) || \
18308  ((INSTANCE) == TIM15))
18309 
18310 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
18311 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18312  ((INSTANCE) == TIM2) || \
18313  ((INSTANCE) == TIM3) || \
18314  ((INSTANCE) == TIM4) || \
18315  ((INSTANCE) == TIM5) || \
18316  ((INSTANCE) == TIM8) || \
18317  ((INSTANCE) == TIM15))
18318 
18319 /****************** TIM Instances : supporting OCxREF clear *******************/
18320 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18321  ((INSTANCE) == TIM2) || \
18322  ((INSTANCE) == TIM3) || \
18323  ((INSTANCE) == TIM4) || \
18324  ((INSTANCE) == TIM5) || \
18325  ((INSTANCE) == TIM8))
18326 
18327 /****************** TIM Instances : remapping capability **********************/
18328 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18329  ((INSTANCE) == TIM2) || \
18330  ((INSTANCE) == TIM3) || \
18331  ((INSTANCE) == TIM8) || \
18332  ((INSTANCE) == TIM15) || \
18333  ((INSTANCE) == TIM16) || \
18334  ((INSTANCE) == TIM17))
18335 
18336 /****************** TIM Instances : supporting repetition counter *************/
18337 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18338  ((INSTANCE) == TIM8) || \
18339  ((INSTANCE) == TIM15) || \
18340  ((INSTANCE) == TIM16) || \
18341  ((INSTANCE) == TIM17))
18342 
18343 /****************** TIM Instances : supporting synchronization ****************/
18344 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
18345 
18346 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
18347 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18348  ((INSTANCE) == TIM8))
18349 
18350 /******************* TIM Instances : Timer input XOR function *****************/
18351 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18352  ((INSTANCE) == TIM2) || \
18353  ((INSTANCE) == TIM3) || \
18354  ((INSTANCE) == TIM4) || \
18355  ((INSTANCE) == TIM5) || \
18356  ((INSTANCE) == TIM8) || \
18357  ((INSTANCE) == TIM15))
18358 
18359 /****************** TIM Instances : Advanced timer instances *******************/
18360 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18361  ((INSTANCE) == TIM8))
18362 
18363 /****************************** TSC Instances *********************************/
18364 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
18365 
18366 /******************** USART Instances : Synchronous mode **********************/
18367 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18368  ((INSTANCE) == USART2) || \
18369  ((INSTANCE) == USART3))
18370 
18371 /******************** UART Instances : Asynchronous mode **********************/
18372 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18373  ((INSTANCE) == USART2) || \
18374  ((INSTANCE) == USART3) || \
18375  ((INSTANCE) == UART4) || \
18376  ((INSTANCE) == UART5))
18377 
18378 /****************** UART Instances : Auto Baud Rate detection ****************/
18379 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18380  ((INSTANCE) == USART2) || \
18381  ((INSTANCE) == USART3) || \
18382  ((INSTANCE) == UART4) || \
18383  ((INSTANCE) == UART5))
18384 
18385 /****************** UART Instances : Driver Enable *****************/
18386 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18387  ((INSTANCE) == USART2) || \
18388  ((INSTANCE) == USART3) || \
18389  ((INSTANCE) == UART4) || \
18390  ((INSTANCE) == UART5) || \
18391  ((INSTANCE) == LPUART1))
18392 
18393 /******************** UART Instances : Half-Duplex mode **********************/
18394 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18395  ((INSTANCE) == USART2) || \
18396  ((INSTANCE) == USART3) || \
18397  ((INSTANCE) == UART4) || \
18398  ((INSTANCE) == UART5) || \
18399  ((INSTANCE) == LPUART1))
18400 
18401 /****************** UART Instances : Hardware Flow control ********************/
18402 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18403  ((INSTANCE) == USART2) || \
18404  ((INSTANCE) == USART3) || \
18405  ((INSTANCE) == UART4) || \
18406  ((INSTANCE) == UART5) || \
18407  ((INSTANCE) == LPUART1))
18408 
18409 /******************** UART Instances : LIN mode **********************/
18410 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18411  ((INSTANCE) == USART2) || \
18412  ((INSTANCE) == USART3) || \
18413  ((INSTANCE) == UART4) || \
18414  ((INSTANCE) == UART5))
18415 
18416 /******************** UART Instances : Wake-up from Stop mode **********************/
18417 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18418  ((INSTANCE) == USART2) || \
18419  ((INSTANCE) == USART3) || \
18420  ((INSTANCE) == UART4) || \
18421  ((INSTANCE) == UART5) || \
18422  ((INSTANCE) == LPUART1))
18423 
18424 /*********************** UART Instances : IRDA mode ***************************/
18425 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18426  ((INSTANCE) == USART2) || \
18427  ((INSTANCE) == USART3) || \
18428  ((INSTANCE) == UART4) || \
18429  ((INSTANCE) == UART5))
18430 
18431 /********************* USART Instances : Smard card mode ***********************/
18432 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18433  ((INSTANCE) == USART2) || \
18434  ((INSTANCE) == USART3))
18435 
18436 /******************** LPUART Instance *****************************************/
18437 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
18438 
18439 /****************************** IWDG Instances ********************************/
18440 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
18441 
18442 /****************************** WWDG Instances ********************************/
18443 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
18444 
18450 /******************************************************************************/
18451 /* For a painless codes migration between the STM32L4xx device product */
18452 /* lines, the aliases defined below are put in place to overcome the */
18453 /* differences in the interrupt handlers and IRQn definitions. */
18454 /* No need to update developed interrupt code when moving across */
18455 /* product lines within the same STM32L4 Family */
18456 /******************************************************************************/
18457 
18458 /* Aliases for __IRQn */
18459 #define TIM6_IRQn TIM6_DAC_IRQn
18460 #define ADC1_IRQn ADC1_2_IRQn
18461 #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
18462 #define TIM8_IRQn TIM8_UP_IRQn
18463 #define HASH_RNG_IRQn RNG_IRQn
18464 #define DFSDM0_IRQn DFSDM1_FLT0_IRQn
18465 #define DFSDM1_IRQn DFSDM1_FLT1_IRQn
18466 #define DFSDM2_IRQn DFSDM1_FLT2_IRQn
18467 #define DFSDM3_IRQn DFSDM1_FLT3_IRQn
18468 
18469 /* Aliases for __IRQHandler */
18470 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
18471 #define ADC1_IRQHandler ADC1_2_IRQHandler
18472 #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
18473 #define TIM8_IRQHandler TIM8_UP_IRQHandler
18474 #define HASH_RNG_IRQHandler RNG_IRQHandler
18475 #define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
18476 #define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
18477 #define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
18478 #define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
18479 
18480 #ifdef __cplusplus
18481 }
18482 #endif /* __cplusplus */
18483 
18484 #endif /* __STM32L476xx_H */
18485 
18494 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32l476xx.h:135
RCC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32l476xx.h:725
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32l476xx.h:162
FIREWALL_TypeDef
Firewall.
Definition: stm32l476xx.h:471
LCD_TypeDef
LCD.
Definition: stm32l476xx.h:601
USB_OTG_OUTEndpointTypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition: stm32l476xx.h:1104
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32l476xx.h:810
TIM1_UP_TIM16_IRQn
@ TIM1_UP_TIM16_IRQn
Definition: stm32l476xx.h:120
DFSDM_Filter_TypeDef::FLTAWHTR
__IO uint32_t FLTAWHTR
Definition: stm32l476xx.h:381
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32l476xx.h:168
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32l476xx.h:918
FLASH_TypeDef::WRP2BR
__IO uint32_t WRP2BR
Definition: stm32l476xx.h:508
USB_OTG_DeviceTypeDef::DINEP1MSK
__IO uint32_t DINEP1MSK
Definition: stm32l476xx.h:1074
DFSDM_Filter_TypeDef::FLTEXMIN
__IO uint32_t FLTEXMIN
Definition: stm32l476xx.h:386
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32l476xx.h:91
PWR_TypeDef::PUCRH
__IO uint32_t PUCRH
Definition: stm32l476xx.h:671
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l476xx.h:572
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32l476xx.h:291
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32l476xx.h:253
USB_OTG_DeviceTypeDef::DAINT
__IO uint32_t DAINT
Definition: stm32l476xx.h:1063
SDMMC_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition: stm32l476xx.h:833
SWPMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32l476xx.h:882
TSC_TypeDef::IER
__IO uint32_t IER
Definition: stm32l476xx.h:948
USB_OTG_DeviceTypeDef::DTHRCTL
__IO uint32_t DTHRCTL
Definition: stm32l476xx.h:1069
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32l476xx.h:689
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32l476xx.h:574
PWR_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32l476xx.h:656
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition: stm32l476xx.h:933
USB_OTG_HostChannelTypeDef::HCTSIZ
__IO uint32_t HCTSIZ
Definition: stm32l476xx.h:1131
SWPMI_TypeDef::RFL
__IO uint32_t RFL
Definition: stm32l476xx.h:883
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32l476xx.h:333
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32l476xx.h:371
USART3_IRQn
@ USART3_IRQn
Definition: stm32l476xx.h:134
FLASH_TypeDef::PCROP2ER
__IO uint32_t PCROP2ER
Definition: stm32l476xx.h:506
USB_OTG_GlobalTypeDef::GHWCFG1
__IO uint32_t GHWCFG1
Definition: stm32l476xx.h:1039
USB_OTG_OUTEndpointTypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition: stm32l476xx.h:1101
SDMMC_TypeDef::DLEN
__IO uint32_t DLEN
Definition: stm32l476xx.h:842
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32l476xx.h:723
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l476xx.h:912
SAI_TypeDef
Serial Audio Interface.
Definition: stm32l476xx.h:808
USART_TypeDef::TDR
__IO uint16_t TDR
Definition: stm32l476xx.h:982
TSC_TypeDef::IOGCSR
__IO uint32_t IOGCSR
Definition: stm32l476xx.h:959
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition: stm32l476xx.h:157
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition: stm32l476xx.h:935
DMA_TypeDef
Definition: stm32l476xx.h:429
FLASH_TypeDef::RESERVED1
__IO uint32_t RESERVED1
Definition: stm32l476xx.h:498
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32l476xx.h:1060
EXTI_TypeDef::RTSR2
__IO uint32_t RTSR2
Definition: stm32l476xx.h:460
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32l476xx.h:919
RTC_TypeDef::TAMPCR
__IO uint32_t TAMPCR
Definition: stm32l476xx.h:766
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32l476xx.h:88
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32l476xx.h:357
ADC_TypeDef::SQR4
__IO uint32_t SQR4
Definition: stm32l476xx.h:211
OPAMP_TypeDef::LPOTR
__IO uint32_t LPOTR
Definition: stm32l476xx.h:635
PWR_TypeDef::PUCRC
__IO uint32_t PUCRC
Definition: stm32l476xx.h:661
USB_OTG_DeviceTypeDef::Reserved24
uint32_t Reserved24
Definition: stm32l476xx.h:1066
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition: stm32l476xx.h:934
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32l476xx.h:90
RCC_TypeDef::APB1ENR1
__IO uint32_t APB1ENR1
Definition: stm32l476xx.h:726
ADC_TypeDef::TR3
__IO uint32_t TR3
Definition: stm32l476xx.h:206
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition: stm32l476xx.h:618
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32l476xx.h:683
USART_TypeDef::RESERVED4
uint16_t RESERVED4
Definition: stm32l476xx.h:981
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32l476xx.h:393
EXTI_TypeDef::SWIER2
__IO uint32_t SWIER2
Definition: stm32l476xx.h:462
SDMMC_TypeDef::RESP1
__I uint32_t RESP1
Definition: stm32l476xx.h:837
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32l476xx.h:409
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32l476xx.h:775
EXTI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l476xx.h:456
PWR_TypeDef::SCR
__IO uint32_t SCR
Definition: stm32l476xx.h:655
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:820
RTC_TypeDef::BKP25R
__IO uint32_t BKP25R
Definition: stm32l476xx.h:795
USB_OTG_GlobalTypeDef::GHWCFG2
__IO uint32_t GHWCFG2
Definition: stm32l476xx.h:1040
TIM8_TRG_COM_IRQn
@ TIM8_TRG_COM_IRQn
Definition: stm32l476xx.h:140
SDMMC_TypeDef::POWER
__IO uint32_t POWER
Definition: stm32l476xx.h:832
USB_OTG_DeviceTypeDef::DEACHMSK
__IO uint32_t DEACHMSK
Definition: stm32l476xx.h:1072
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32l476xx.h:92
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:593
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32l476xx.h:782
USB_OTG_GlobalTypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition: stm32l476xx.h:1048
TIM1_TRG_COM_TIM17_IRQn
@ TIM1_TRG_COM_TIM17_IRQn
Definition: stm32l476xx.h:121
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32l476xx.h:223
PWR_TypeDef::PUCRD
__IO uint32_t PUCRD
Definition: stm32l476xx.h:663
TIM_TypeDef
TIM.
Definition: stm32l476xx.h:910
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32l476xx.h:265
LCD_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32l476xx.h:607
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32l476xx.h:494
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition: stm32l476xx.h:594
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l476xx.h:431
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32l476xx.h:774
USB_OTG_GlobalTypeDef::GPWRDN
__IO uint32_t GPWRDN
Definition: stm32l476xx.h:1044
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32l476xx.h:302
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:410
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l476xx.h:578
USART_TypeDef::RDR
__IO uint16_t RDR
Definition: stm32l476xx.h:980
DFSDM_Filter_TypeDef::FLTAWSR
__IO uint32_t FLTAWSR
Definition: stm32l476xx.h:383
USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
__IO uint32_t DOEPTSIZ
Definition: stm32l476xx.h:1103
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition: stm32l476xx.h:114
PWR_TypeDef
Power Control.
Definition: stm32l476xx.h:647
USB_OTG_GlobalTypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition: stm32l476xx.h:1023
DBGMCU_TypeDef::APB1FZR1
__IO uint32_t APB1FZR1
Definition: stm32l476xx.h:411
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l476xx.h:816
PWR_TypeDef::PDCRB
__IO uint32_t PDCRB
Definition: stm32l476xx.h:660
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition: stm32l476xx.h:822
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32l476xx.h:1055
USB_OTG_GlobalTypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition: stm32l476xx.h:1032
DMA1_Channel2_IRQn
@ DMA1_Channel2_IRQn
Definition: stm32l476xx.h:107
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32l476xx.h:619
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32l476xx.h:551
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32l476xx.h:555
PWR_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32l476xx.h:654
DFSDM_Channel_TypeDef::CHDATINR
__IO uint32_t CHDATINR
Definition: stm32l476xx.h:400
USB_OTG_GlobalTypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition: stm32l476xx.h:1026
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition: stm32l476xx.h:117
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32l476xx.h:210
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:1014
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32l476xx.h:122
RCC_TypeDef::APB2SMENR
__IO uint32_t APB2SMENR
Definition: stm32l476xx.h:736
LPTIM_TypeDef
LPTIMER.
Definition: stm32l476xx.h:614
TSC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32l476xx.h:956
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32l476xx.h:209
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32l476xx.h:304
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition: stm32l476xx.h:217
EXTI_TypeDef::IMR1
__IO uint32_t IMR1
Definition: stm32l476xx.h:450
PWR_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32l476xx.h:651
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32l476xx.h:160
TSC_TypeDef::IOCCR
__IO uint32_t IOCCR
Definition: stm32l476xx.h:957
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32l476xx.h:167
__IO
#define __IO
Definition: core_cm0.h:213
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32l476xx.h:99
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition: stm32l476xx.h:156
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32l476xx.h:286
ADC_TypeDef::OFR4
__IO uint32_t OFR4
Definition: stm32l476xx.h:220
EXTI_TypeDef::PR1
__IO uint32_t PR1
Definition: stm32l476xx.h:455
SYSCFG_TypeDef::SKR
__IO uint32_t SKR
Definition: stm32l476xx.h:902
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32l476xx.h:754
DFSDM_Channel_TypeDef::CHWDATAR
__IO uint32_t CHWDATAR
Definition: stm32l476xx.h:399
UART5_IRQn
@ UART5_IRQn
Definition: stm32l476xx.h:148
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32l476xx.h:569
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition: stm32l476xx.h:158
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32l476xx.h:534
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32l476xx.h:292
USB_OTG_DeviceTypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition: stm32l476xx.h:1062
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32l476xx.h:785
PVD_PVM_IRQn
@ PVD_PVM_IRQn
Definition: stm32l476xx.h:96
ADC_TypeDef::OFR2
__IO uint32_t OFR2
Definition: stm32l476xx.h:218
FLASH_TypeDef::WRP2AR
__IO uint32_t WRP2AR
Definition: stm32l476xx.h:507
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32l476xx.h:1097
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition: stm32l476xx.h:161
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32l476xx.h:590
TSC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l476xx.h:952
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32l476xx.h:755
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32l476xx.h:89
USB_OTG_HostTypeDef::HFNUM
__IO uint32_t HFNUM
Definition: stm32l476xx.h:1115
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:682
SYSCFG_TypeDef::CFGR1
__IO uint32_t CFGR1
Definition: stm32l476xx.h:897
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32l476xx.h:355
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32l476xx.h:789
PWR_TypeDef::SR1
__IO uint32_t SR1
Definition: stm32l476xx.h:653
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32l476xx.h:592
RCC_TypeDef::CIFR
__IO uint32_t CIFR
Definition: stm32l476xx.h:711
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32l476xx.h:930
RTC_TypeDef::BKP23R
__IO uint32_t BKP23R
Definition: stm32l476xx.h:793
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:1013
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32l476xx.h:276
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32l476xx.h:765
EXTI_TypeDef::SWIER1
__IO uint32_t SWIER1
Definition: stm32l476xx.h:454
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32l476xx.h:129
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32l476xx.h:690
USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: stm32l476xx.h:1033
USB_OTG_GlobalTypeDef::GRXSTSR
__IO uint32_t GRXSTSR
Definition: stm32l476xx.h:1030
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32l476xx.h:622
USB_OTG_INEndpointTypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition: stm32l476xx.h:1089
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32l476xx.h:127
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32l476xx.h:125
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition: stm32l476xx.h:576
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32l476xx.h:251
SAI2_IRQn
@ SAI2_IRQn
Definition: stm32l476xx.h:170
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32l476xx.h:194
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32l476xx.h:349
ADC_Common_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32l476xx.h:239
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32l476xx.h:715
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32l476xx.h:136
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32l476xx.h:751
SWPMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l476xx.h:881
DMA2_Channel1_IRQn
@ DMA2_Channel1_IRQn
Definition: stm32l476xx.h:151
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32l476xx.h:298
PWR_TypeDef::PDCRC
__IO uint32_t PDCRC
Definition: stm32l476xx.h:662
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:334
PWR_TypeDef::PUCRA
__IO uint32_t PUCRA
Definition: stm32l476xx.h:657
DFSDM_Filter_TypeDef::FLTFCR
__IO uint32_t FLTFCR
Definition: stm32l476xx.h:378
USART2_IRQn
@ USART2_IRQn
Definition: stm32l476xx.h:133
RCC_TypeDef::APB1RSTR2
__IO uint32_t APB1RSTR2
Definition: stm32l476xx.h:719
FLASH_TypeDef::WRP1AR
__IO uint32_t WRP1AR
Definition: stm32l476xx.h:502
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32l476xx.h:929
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32l476xx.h:208
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32l476xx.h:87
SDMMC_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition: stm32l476xx.h:841
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32l476xx.h:631
LCD_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32l476xx.h:604
__I
#define __I
Definition: core_cm0.h:210
USB_OTG_HostChannelTypeDef::HCSPLT
__IO uint32_t HCSPLT
Definition: stm32l476xx.h:1128
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32l476xx.h:692
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32l476xx.h:925
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32l476xx.h:923
SWPMI_TypeDef::OR
__IO uint32_t OR
Definition: stm32l476xx.h:886
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l476xx.h:238
DFSDM_Filter_TypeDef::FLTEXMAX
__IO uint32_t FLTEXMAX
Definition: stm32l476xx.h:385
EXTI_TypeDef::FTSR1
__IO uint32_t FTSR1
Definition: stm32l476xx.h:453
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32l476xx.h:864
FMC_Bank3_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:537
DMA1_Channel1_IRQn
@ DMA1_Channel1_IRQn
Definition: stm32l476xx.h:106
TSC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32l476xx.h:958
SWPMI_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32l476xx.h:878
OPAMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l476xx.h:640
USB_OTG_GlobalTypeDef::GADPCTL
__IO uint32_t GADPCTL
Definition: stm32l476xx.h:1046
RTC_TypeDef::BKP29R
__IO uint32_t BKP29R
Definition: stm32l476xx.h:799
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32l476xx.h:215
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32l476xx.h:914
TSC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l476xx.h:954
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition: stm32l476xx.h:116
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32l476xx.h:915
USB_OTG_GlobalTypeDef::GHWCFG3
__IO uint32_t GHWCFG3
Definition: stm32l476xx.h:1041
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32l476xx.h:713
ADC_TypeDef::TR2
__IO uint32_t TR2
Definition: stm32l476xx.h:205
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32l476xx.h:285
RCC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l476xx.h:717
FIREWALL_TypeDef::CSL
__IO uint32_t CSL
Definition: stm32l476xx.h:474
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32l476xx.h:573
DBGMCU_TypeDef::APB1FZR2
__IO uint32_t APB1FZR2
Definition: stm32l476xx.h:412
RTC_TypeDef::BKP24R
__IO uint32_t BKP24R
Definition: stm32l476xx.h:794
DFSDM_Filter_TypeDef::FLTISR
__IO uint32_t FLTISR
Definition: stm32l476xx.h:375
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32l476xx.h:169
FLASH_TypeDef::PCROP2SR
__IO uint32_t PCROP2SR
Definition: stm32l476xx.h:505
SYSCFG_TypeDef
System configuration controller.
Definition: stm32l476xx.h:894
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32l476xx.h:819
FLASH_TypeDef::WRP1BR
__IO uint32_t WRP1BR
Definition: stm32l476xx.h:503
USB_OTG_HostChannelTypeDef::HCINT
__IO uint32_t HCINT
Definition: stm32l476xx.h:1129
DFSDM_Filter_TypeDef::FLTCR1
__IO uint32_t FLTCR1
Definition: stm32l476xx.h:373
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32l476xx.h:867
SDMMC_TypeDef::FIFO
__IO uint32_t FIFO
Definition: stm32l476xx.h:851
RCC_TypeDef::CCIPR
__IO uint32_t CCIPR
Definition: stm32l476xx.h:738
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32l476xx.h:788
RTC_TypeDef::BKP20R
__IO uint32_t BKP20R
Definition: stm32l476xx.h:790
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32l476xx.h:344
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32l476xx.h:102
RCC_TypeDef::APB1ENR2
__IO uint32_t APB1ENR2
Definition: stm32l476xx.h:727
PWR_TypeDef::PDCRF
__IO uint32_t PDCRF
Definition: stm32l476xx.h:668
USB_OTG_DeviceTypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition: stm32l476xx.h:1061
TSC_TypeDef::IOSCR
__IO uint32_t IOSCR
Definition: stm32l476xx.h:955
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32l476xx.h:591
USB_OTG_HostTypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition: stm32l476xx.h:1117
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32l476xx.h:716
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32l476xx.h:201
PWR_TypeDef::CR4
__IO uint32_t CR4
Definition: stm32l476xx.h:652
USB_OTG_GlobalTypeDef
USB_OTG_Core_register.
Definition: stm32l476xx.h:1021
SYSCFG_TypeDef::SCSR
__IO uint32_t SCSR
Definition: stm32l476xx.h:899
SYSCFG_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32l476xx.h:900
USB_OTG_GlobalTypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition: stm32l476xx.h:1024
USB_OTG_DeviceTypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition: stm32l476xx.h:1064
USART1_IRQn
@ USART1_IRQn
Definition: stm32l476xx.h:132
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32l476xx.h:1003
ADC_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32l476xx.h:230
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32l476xx.h:917
FLASH_TypeDef::PCROP1ER
__IO uint32_t PCROP1ER
Definition: stm32l476xx.h:501
DAC_TypeDef::SHSR1
__IO uint32_t SHSR1
Definition: stm32l476xx.h:362
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32l476xx.h:525
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32l476xx.h:557
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32l476xx.h:762
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32l476xx.h:685
LCD_TypeDef::CLR
__IO uint32_t CLR
Definition: stm32l476xx.h:606
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32l476xx.h:141
DFSDM_Filter_TypeDef::FLTICR
__IO uint32_t FLTICR
Definition: stm32l476xx.h:376
ADC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:198
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32l476xx.h:493
ADC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32l476xx.h:214
SDMMC_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition: stm32l476xx.h:843
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l476xx.h:815
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32l476xx.h:254
FIREWALL_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l476xx.h:480
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32l476xx.h:356
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32l476xx.h:202
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32l476xx.h:760
SDMMC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l476xx.h:846
USB_OTG_HostTypeDef::HCFG
__IO uint32_t HCFG
Definition: stm32l476xx.h:1113
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32l476xx.h:421
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition: stm32l476xx.h:1090
OPAMP_Common_TypeDef
Definition: stm32l476xx.h:638
ADC_TypeDef::IER
__IO uint32_t IER
Definition: stm32l476xx.h:197
DMA1_Channel5_IRQn
@ DMA1_Channel5_IRQn
Definition: stm32l476xx.h:110
USB_OTG_HostChannelTypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition: stm32l476xx.h:1130
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32l476xx.h:413
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32l476xx.h:707
RCC_TypeDef
Reset and Clock Control.
Definition: stm32l476xx.h:702
GPIO_TypeDef
General Purpose I/O.
Definition: stm32l476xx.h:548
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32l476xx.h:1015
PWR_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l476xx.h:649
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32l476xx.h:352
SDMMC_TypeDef::DCOUNT
__I uint32_t DCOUNT
Definition: stm32l476xx.h:844
UART4_IRQn
@ UART4_IRQn
Definition: stm32l476xx.h:147
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32l476xx.h:556
DMA1_Channel3_IRQn
@ DMA1_Channel3_IRQn
Definition: stm32l476xx.h:108
FMC_Bank3_TypeDef::PATT
__IO uint32_t PATT
Definition: stm32l476xx.h:539
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32l476xx.h:101
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32l476xx.h:212
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition: stm32l476xx.h:171
CRC_TypeDef::POL
__IO uint32_t POL
Definition: stm32l476xx.h:337
USB_OTG_HostTypeDef::Reserved40C
uint32_t Reserved40C
Definition: stm32l476xx.h:1116
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition: stm32l476xx.h:1065
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:863
RCC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32l476xx.h:739
SDMMC_TypeDef::RESPCMD
__I uint32_t RESPCMD
Definition: stm32l476xx.h:836
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32l476xx.h:778
DMA2_Channel2_IRQn
@ DMA2_Channel2_IRQn
Definition: stm32l476xx.h:152
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:496
TSC_TypeDef::IOASCR
__IO uint32_t IOASCR
Definition: stm32l476xx.h:953
TSC_TypeDef
Touch Sensing Controller (TSC)
Definition: stm32l476xx.h:945
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32l476xx.h:448
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32l476xx.h:85
RTC_TypeDef
Real-Time Clock.
Definition: stm32l476xx.h:748
DFSDM_Filter_TypeDef::FLTAWCFR
__IO uint32_t FLTAWCFR
Definition: stm32l476xx.h:384
PWR_TypeDef::PDCRH
__IO uint32_t PDCRH
Definition: stm32l476xx.h:672
USART_TypeDef::RESERVED3
uint16_t RESERVED3
Definition: stm32l476xx.h:977
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32l476xx.h:118
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:359
USB_OTG_OUTEndpointTypeDef::DOEPCTL
__IO uint32_t DOEPCTL
Definition: stm32l476xx.h:1099
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32l476xx.h:724
COMP_TypeDef
Comparator.
Definition: stm32l476xx.h:314
FIREWALL_TypeDef::NVDSL
__IO uint32_t NVDSL
Definition: stm32l476xx.h:476
ADC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32l476xx.h:229
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32l476xx.h:150
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32l476xx.h:693
TSC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:947
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32l476xx.h:124
DMA_Request_TypeDef
Definition: stm32l476xx.h:435
FIREWALL_TypeDef::VDSSA
__IO uint32_t VDSSA
Definition: stm32l476xx.h:477
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32l476xx.h:95
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32l476xx.h:142
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32l476xx.h:706
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32l476xx.h:303
USB_OTG_GlobalTypeDef::GINTMSK
__IO uint32_t GINTMSK
Definition: stm32l476xx.h:1029
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32l476xx.h:927
FMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32l476xx.h:540
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition: stm32l476xx.h:336
EXTI_TypeDef::EMR1
__IO uint32_t EMR1
Definition: stm32l476xx.h:451
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32l476xx.h:348
FIREWALL_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l476xx.h:479
DFSDM_Filter_TypeDef::FLTAWLTR
__IO uint32_t FLTAWLTR
Definition: stm32l476xx.h:382
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition: stm32l476xx.h:579
RTC_TypeDef::BKP28R
__IO uint32_t BKP28R
Definition: stm32l476xx.h:798
USB_OTG_GlobalTypeDef::GLPMCFG
__IO uint32_t GLPMCFG
Definition: stm32l476xx.h:1043
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition: stm32l476xx.h:1076
DAC_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32l476xx.h:361
ADC_TypeDef::AWD2CR
__IO uint32_t AWD2CR
Definition: stm32l476xx.h:227
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32l476xx.h:866
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32l476xx.h:103
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32l476xx.h:290
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l476xx.h:970
PWR_TypeDef::PUCRB
__IO uint32_t PUCRB
Definition: stm32l476xx.h:659
GPIO_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32l476xx.h:559
USB_OTG_DeviceTypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition: stm32l476xx.h:1068
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32l476xx.h:224
USB_OTG_GlobalTypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition: stm32l476xx.h:1025
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32l476xx.h:86
PWR_TypeDef::PDCRG
__IO uint32_t PDCRG
Definition: stm32l476xx.h:670
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32l476xx.h:553
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32l476xx.h:1100
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32l476xx.h:680
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32l476xx.h:222
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:1004
EXTI_TypeDef::PR2
__IO uint32_t PR2
Definition: stm32l476xx.h:463
RTC_TypeDef::BKP22R
__IO uint32_t BKP22R
Definition: stm32l476xx.h:792
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32l476xx.h:200
USB_OTG_INEndpointTypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition: stm32l476xx.h:1086
FLASH_TypeDef::OPTR
__IO uint32_t OPTR
Definition: stm32l476xx.h:499
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:752
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32l476xx.h:581
EXTI_TypeDef::IMR2
__IO uint32_t IMR2
Definition: stm32l476xx.h:458
USART_TypeDef::RQR
__IO uint16_t RQR
Definition: stm32l476xx.h:976
EXTI_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l476xx.h:457
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32l476xx.h:722
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32l476xx.h:761
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32l476xx.h:859
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l476xx.h:969
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32l476xx.h:776
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l476xx.h:196
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32l476xx.h:971
TIM8_BRK_IRQn
@ TIM8_BRK_IRQn
Definition: stm32l476xx.h:138
RCC_TypeDef::PLLSAI2CFGR
__IO uint32_t PLLSAI2CFGR
Definition: stm32l476xx.h:709
DMA1_Channel7_IRQn
@ DMA1_Channel7_IRQn
Definition: stm32l476xx.h:112
USART_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l476xx.h:978
SDMMC_TypeDef::RESP3
__I uint32_t RESP3
Definition: stm32l476xx.h:839
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32l476xx.h:275
USART_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l476xx.h:979
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32l476xx.h:1125
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32l476xx.h:93
OPAMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l476xx.h:633
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l476xx.h:616
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32l476xx.h:921
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition: stm32l476xx.h:817
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition: stm32l476xx.h:1091
USB_OTG_HostChannelTypeDef::HCDMA
__IO uint32_t HCDMA
Definition: stm32l476xx.h:1132
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32l476xx.h:575
DFSDM_Channel_TypeDef::CHCFGR2
__IO uint32_t CHCFGR2
Definition: stm32l476xx.h:396
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32l476xx.h:1111
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32l476xx.h:261
DMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition: stm32l476xx.h:425
FPU_IRQn
@ FPU_IRQn
Definition: stm32l476xx.h:175
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:916
PWR_TypeDef::PDCRE
__IO uint32_t PDCRE
Definition: stm32l476xx.h:666
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32l476xx.h:123
LCD_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:605
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32l476xx.h:131
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32l476xx.h:241
ADC_TypeDef::TR1
__IO uint32_t TR1
Definition: stm32l476xx.h:204
USB_OTG_DeviceTypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition: stm32l476xx.h:1067
TIM_TypeDef::OR2
__IO uint32_t OR2
Definition: stm32l476xx.h:936
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32l476xx.h:1082
PWR_TypeDef::PUCRF
__IO uint32_t PUCRF
Definition: stm32l476xx.h:667
RTC_TypeDef::BKP21R
__IO uint32_t BKP21R
Definition: stm32l476xx.h:791
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l476xx.h:299
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32l476xx.h:491
DFSDM_Channel_TypeDef::CHCFGR1
__IO uint32_t CHCFGR1
Definition: stm32l476xx.h:395
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32l476xx.h:353
PWR_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l476xx.h:650
COMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l476xx.h:316
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32l476xx.h:554
DMA_Request_TypeDef::CSELR
__IO uint32_t CSELR
Definition: stm32l476xx.h:437
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32l476xx.h:1000
DMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition: stm32l476xx.h:424
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: stm32l476xx.h:1119
FMC_IRQn
@ FMC_IRQn
Definition: stm32l476xx.h:143
LCD_IRQn
@ LCD_IRQn
Definition: stm32l476xx.h:173
RCC_TypeDef::CICR
__IO uint32_t CICR
Definition: stm32l476xx.h:712
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32l476xx.h:146
DMA2_Channel7_IRQn
@ DMA2_Channel7_IRQn
Definition: stm32l476xx.h:164
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition: stm32l476xx.h:975
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32l476xx.h:759
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32l476xx.h:896
DMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l476xx.h:423
SWPMI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l476xx.h:879
RCC_TypeDef::AHB3SMENR
__IO uint32_t AHB3SMENR
Definition: stm32l476xx.h:732
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32l476xx.h:432
DFSDM_Channel_TypeDef::CHAWSCDR
__IO uint32_t CHAWSCDR
Definition: stm32l476xx.h:397
USB_OTG_GlobalTypeDef::GINTSTS
__IO uint32_t GINTSTS
Definition: stm32l476xx.h:1028
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:620
RTC_TypeDef::OR
__IO uint32_t OR
Definition: stm32l476xx.h:769
DMA1_Channel6_IRQn
@ DMA1_Channel6_IRQn
Definition: stm32l476xx.h:111
GPIO_TypeDef::ASCR
__IO uint32_t ASCR
Definition: stm32l476xx.h:560
TSC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l476xx.h:949
PWR_TypeDef::PUCRG
__IO uint32_t PUCRG
Definition: stm32l476xx.h:669
DMA1_Channel4_IRQn
@ DMA1_Channel4_IRQn
Definition: stm32l476xx.h:109
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32l476xx.h:967
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition: stm32l476xx.h:821
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32l476xx.h:347
USB_OTG_GlobalTypeDef::HNPTXSTS
__IO uint32_t HNPTXSTS
Definition: stm32l476xx.h:1034
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32l476xx.h:350
EXTI_TypeDef::RTSR1
__IO uint32_t RTSR1
Definition: stm32l476xx.h:452
DMA2_Channel5_IRQn
@ DMA2_Channel5_IRQn
Definition: stm32l476xx.h:155
SDMMC_TypeDef::RESP2
__I uint32_t RESP2
Definition: stm32l476xx.h:838
RCC_TypeDef::APB1SMENR1
__IO uint32_t APB1SMENR1
Definition: stm32l476xx.h:734
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32l476xx.h:714
RCC_IRQn
@ RCC_IRQn
Definition: stm32l476xx.h:100
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32l476xx.h:786
COMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l476xx.h:321
USART_TypeDef::RESERVED5
uint16_t RESERVED5
Definition: stm32l476xx.h:983
system_stm32l4xx.h
CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
ADC_TypeDef::OFR3
__IO uint32_t OFR3
Definition: stm32l476xx.h:219
DMA2_Channel3_IRQn
@ DMA2_Channel3_IRQn
Definition: stm32l476xx.h:153
ADC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l476xx.h:207
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32l476xx.h:516
SWPMI_TypeDef::RDR
__IO uint32_t RDR
Definition: stm32l476xx.h:885
RCC_TypeDef::AHB1SMENR
__IO uint32_t AHB1SMENR
Definition: stm32l476xx.h:730
FLASH_TypeDef::PCROP1SR
__IO uint32_t PCROP1SR
Definition: stm32l476xx.h:500
RTC_TypeDef::BKP27R
__IO uint32_t BKP27R
Definition: stm32l476xx.h:797
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32l476xx.h:768
TIM_TypeDef::OR1
__IO uint32_t OR1
Definition: stm32l476xx.h:932
USB_OTG_DeviceTypeDef::DCFG
__IO uint32_t DCFG
Definition: stm32l476xx.h:1057
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:495
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32l476xx.h:98
FLASH_TypeDef
FLASH Registers.
Definition: stm32l476xx.h:489
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32l476xx.h:300
DFSDM_Filter_TypeDef::FLTJDATAR
__IO uint32_t FLTJDATAR
Definition: stm32l476xx.h:379
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32l476xx.h:780
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32l476xx.h:104
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l476xx.h:861
DBGMCU_TypeDef
Debug MCU.
Definition: stm32l476xx.h:407
SDMMC_TypeDef::ARG
__IO uint32_t ARG
Definition: stm32l476xx.h:834
FIREWALL_TypeDef::CSSA
__IO uint32_t CSSA
Definition: stm32l476xx.h:473
USB_OTG_INEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32l476xx.h:1087
FLASH_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32l476xx.h:497
SYSCFG_TypeDef::SWPR
__IO uint32_t SWPR
Definition: stm32l476xx.h:901
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32l476xx.h:1102
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32l476xx.h:552
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32l476xx.h:777
TSC_IRQn
@ TSC_IRQn
Definition: stm32l476xx.h:172
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32l476xx.h:617
VREFBUF_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l476xx.h:992
FMC_Bank3_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32l476xx.h:536
USB_OTG_GlobalTypeDef::GRXSTSP
__IO uint32_t GRXSTSP
Definition: stm32l476xx.h:1031
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition: stm32l476xx.h:1073
DAC_TypeDef::SHHR
__IO uint32_t SHHR
Definition: stm32l476xx.h:364
DAC_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l476xx.h:360
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32l476xx.h:263
USB_OTG_HostTypeDef::HAINT
__IO uint32_t HAINT
Definition: stm32l476xx.h:1118
PWR_TypeDef::PUCRE
__IO uint32_t PUCRE
Definition: stm32l476xx.h:665
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32l476xx.h:729
VREFBUF_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l476xx.h:993
RCC_TypeDef::RESERVED6
uint32_t RESERVED6
Definition: stm32l476xx.h:737
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32l476xx.h:694
RCC_TypeDef::ICSCR
__IO uint32_t ICSCR
Definition: stm32l476xx.h:705
IRQn_Type
IRQn_Type
STM32L4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32l476xx.h:82
RCC_TypeDef::AHB2SMENR
__IO uint32_t AHB2SMENR
Definition: stm32l476xx.h:731
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l476xx.h:721
ADC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32l476xx.h:213
RCC_TypeDef::RESERVED5
uint32_t RESERVED5
Definition: stm32l476xx.h:733
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l476xx.h:687
SDMMC_TypeDef::FIFOCNT
__I uint32_t FIFOCNT
Definition: stm32l476xx.h:849
USB_OTG_GlobalTypeDef::Reserved6
uint32_t Reserved6
Definition: stm32l476xx.h:1042
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32l476xx.h:273
DMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition: stm32l476xx.h:426
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32l476xx.h:331
USART_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32l476xx.h:974
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32l476xx.h:225
FIREWALL_TypeDef::NVDSSA
__IO uint32_t NVDSSA
Definition: stm32l476xx.h:475
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition: stm32l476xx.h:115
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32l476xx.h:772
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition: stm32l476xx.h:166
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition: stm32l476xx.h:621
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32l476xx.h:684
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition: stm32l476xx.h:231
USB_OTG_GlobalTypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition: stm32l476xx.h:1027
ADC_Common_TypeDef
Definition: stm32l476xx.h:236
DAC_TypeDef::SHRR
__IO uint32_t SHRR
Definition: stm32l476xx.h:365
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32l476xx.h:691
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:1002
PWR_TypeDef::PDCRA
__IO uint32_t PDCRA
Definition: stm32l476xx.h:658
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32l476xx.h:330
SDMMC_TypeDef::MASK
__IO uint32_t MASK
Definition: stm32l476xx.h:847
FMC_Bank3_TypeDef::PMEM
__IO uint32_t PMEM
Definition: stm32l476xx.h:538
USB_OTG_HostTypeDef::HFIR
__IO uint32_t HFIR
Definition: stm32l476xx.h:1114
SDMMC_TypeDef::STA
__I uint32_t STA
Definition: stm32l476xx.h:845
SAI_Block_TypeDef
Definition: stm32l476xx.h:813
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32l476xx.h:144
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32l476xx.h:571
USB_OTG_INEndpointTypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition: stm32l476xx.h:1088
SWPMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:877
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:346
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32l476xx.h:740
USB_OTG_INEndpointTypeDef::DIEPCTL
__IO uint32_t DIEPCTL
Definition: stm32l476xx.h:1084
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32l476xx.h:252
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32l476xx.h:332
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition: stm32l476xx.h:875
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32l476xx.h:105
RTC_TypeDef::reserved
uint32_t reserved
Definition: stm32l476xx.h:756
USB_OTG_DeviceTypeDef::DCTL
__IO uint32_t DCTL
Definition: stm32l476xx.h:1058
SDMMC_TypeDef
Secure digital input/output Interface.
Definition: stm32l476xx.h:830
USB_OTG_GlobalTypeDef::GSNPSID
__IO uint32_t GSNPSID
Definition: stm32l476xx.h:1038
RTC_TypeDef::BKP30R
__IO uint32_t BKP30R
Definition: stm32l476xx.h:800
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32l476xx.h:926
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32l476xx.h:266
ADC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32l476xx.h:203
DFSDM_Filter_TypeDef::FLTCNVTIMR
__IO uint32_t FLTCNVTIMR
Definition: stm32l476xx.h:387
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32l476xx.h:130
FLASH_TypeDef::PDKEYR
__IO uint32_t PDKEYR
Definition: stm32l476xx.h:492
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32l476xx.h:297
EXTI_TypeDef::FTSR2
__IO uint32_t FTSR2
Definition: stm32l476xx.h:461
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l476xx.h:913
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32l476xx.h:770
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32l476xx.h:289
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32l476xx.h:750
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32l476xx.h:741
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32l476xx.h:550
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32l476xx.h:240
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32l476xx.h:580
DAC_TypeDef::SHSR2
__IO uint32_t SHSR2
Definition: stm32l476xx.h:363
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32l476xx.h:924
RTC_TypeDef::BKP26R
__IO uint32_t BKP26R
Definition: stm32l476xx.h:796
RCC_TypeDef::APB1SMENR2
__IO uint32_t APB1SMENR2
Definition: stm32l476xx.h:735
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32l476xx.h:145
RNG_IRQn
@ RNG_IRQn
Definition: stm32l476xx.h:174
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32l476xx.h:773
CRC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32l476xx.h:335
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32l476xx.h:199
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32l476xx.h:920
USB_OTG_DeviceTypeDef::DEACHINT
__IO uint32_t DEACHINT
Definition: stm32l476xx.h:1071
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32l476xx.h:781
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32l476xx.h:758
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32l476xx.h:128
DFSDM_Filter_TypeDef::FLTCR2
__IO uint32_t FLTCR2
Definition: stm32l476xx.h:374
DMA2_Channel4_IRQn
@ DMA2_Channel4_IRQn
Definition: stm32l476xx.h:154
RTC_TypeDef::BKP31R
__IO uint32_t BKP31R
Definition: stm32l476xx.h:801
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32l476xx.h:757
OPAMP_TypeDef::OTR
__IO uint32_t OTR
Definition: stm32l476xx.h:634
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l476xx.h:753
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32l476xx.h:764
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32l476xx.h:1085
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32l476xx.h:787
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32l476xx.h:354
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:704
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32l476xx.h:97
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32l476xx.h:351
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32l476xx.h:972
ADC_TypeDef::AWD3CR
__IO uint32_t AWD3CR
Definition: stm32l476xx.h:228
TIM1_BRK_TIM15_IRQn
@ TIM1_BRK_TIM15_IRQn
Definition: stm32l476xx.h:119
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32l476xx.h:720
USB_OTG_HostChannelTypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition: stm32l476xx.h:1127
TSC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l476xx.h:950
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32l476xx.h:922
DFSDM_Filter_TypeDef::FLTJCHGR
__IO uint32_t FLTJCHGR
Definition: stm32l476xx.h:377
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l476xx.h:577
VREFBUF_TypeDef
VREFBUF.
Definition: stm32l476xx.h:990
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32l476xx.h:862
TIM8_UP_IRQn
@ TIM8_UP_IRQn
Definition: stm32l476xx.h:139
CAN_TypeDef
Controller Area Network.
Definition: stm32l476xx.h:283
USB_OTG_GlobalTypeDef::CID
__IO uint32_t CID
Definition: stm32l476xx.h:1037
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32l476xx.h:728
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32l476xx.h:358
LPTIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32l476xx.h:624
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition: stm32l476xx.h:137
USART_TypeDef::GTPR
__IO uint16_t GTPR
Definition: stm32l476xx.h:973
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition: stm32l476xx.h:232
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32l476xx.h:686
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32l476xx.h:931
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32l476xx.h:771
COMP_IRQn
@ COMP_IRQn
Definition: stm32l476xx.h:159
USB_OTG_GlobalTypeDef::GDFIFOCFG
__IO uint32_t GDFIFOCFG
Definition: stm32l476xx.h:1045
EXTI_TypeDef::EMR2
__IO uint32_t EMR2
Definition: stm32l476xx.h:459
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32l476xx.h:623
SDMMC_TypeDef::CMD
__IO uint32_t CMD
Definition: stm32l476xx.h:835
USB_OTG_DeviceTypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition: stm32l476xx.h:1070
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32l476xx.h:767
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32l476xx.h:865
SDMMC_TypeDef::RESP4
__I uint32_t RESP4
Definition: stm32l476xx.h:840
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32l476xx.h:126
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32l476xx.h:301
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32l476xx.h:688
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32l476xx.h:264
TIM_TypeDef::OR3
__IO uint32_t OR3
Definition: stm32l476xx.h:937
SWPMI_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32l476xx.h:880
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32l476xx.h:149
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32l476xx.h:165
USB_OTG_GlobalTypeDef::GCCFG
__IO uint32_t GCCFG
Definition: stm32l476xx.h:1036
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32l476xx.h:928
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32l476xx.h:288
COMP_Common_TypeDef
Definition: stm32l476xx.h:319
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32l476xx.h:783
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32l476xx.h:588
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32l476xx.h:784
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition: stm32l476xx.h:818
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32l476xx.h:763
FIREWALL_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:481
PWR_TypeDef::PDCRD
__IO uint32_t PDCRD
Definition: stm32l476xx.h:664
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32l476xx.h:287
RCC_TypeDef::PLLSAI1CFGR
__IO uint32_t PLLSAI1CFGR
Definition: stm32l476xx.h:708
FIREWALL_TypeDef::VDSL
__IO uint32_t VDSL
Definition: stm32l476xx.h:478
RCC_TypeDef::APB1RSTR1
__IO uint32_t APB1RSTR1
Definition: stm32l476xx.h:718
CRC_TypeDef
CRC calculation unit.
Definition: stm32l476xx.h:328
FMC_Bank3_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32l476xx.h:541
RCC_TypeDef::CIER
__IO uint32_t CIER
Definition: stm32l476xx.h:710
RNG_TypeDef
RNG.
Definition: stm32l476xx.h:1011
ADC1_2_IRQn
@ ADC1_2_IRQn
Definition: stm32l476xx.h:113
TSC_TypeDef::IOHCR
__IO uint32_t IOHCR
Definition: stm32l476xx.h:951
DFSDM_Filter_TypeDef::FLTRDATAR
__IO uint32_t FLTRDATAR
Definition: stm32l476xx.h:380
DMA2_Channel6_IRQn
@ DMA2_Channel6_IRQn
Definition: stm32l476xx.h:163
SWPMI_TypeDef::TDR
__IO uint32_t TDR
Definition: stm32l476xx.h:884
LCD_TypeDef::CR
__IO uint32_t CR
Definition: stm32l476xx.h:603
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32l476xx.h:779
USB_OTG_DeviceTypeDef::DSTS
__IO uint32_t DSTS
Definition: stm32l476xx.h:1059
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32l476xx.h:249
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